Electronic circuit arrangement for receiving low frequency electro-magnetic waves with an adjustable attenuator element

US2016006497A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016006497-A1
Application numberUS-201514848092-A
CountryUS
Kind codeA1
Filing dateSep 8, 2015
Priority dateNov 17, 2010
Publication dateJan 7, 2016
Grant date

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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An electronic circuit arrangement for receiving low-frequency electromagnetic waves is proposed, having an inductor (L) acting as an antenna for generating a received signal, having a first receiver ( 2 ), connected to the inductor (L), for decoding a first component of the received signal and having a second receiver ( 3 ), connected to the inductor (L), for decoding a second component of the received signal, wherein at least the second receiver ( 3 ) is connected to the inductor (L) via an attenuator element ( 4 ) having adjustable attenuation, wherein at least one adjustment signal generation circuit ( 5, 6 ) is provided for generating an adjustment signal corresponding to a voltage of the received signal which is fed to the attenuator element ( 4 ) for adjusting the attenuation.

First claim

Opening claim text (preview).

We claim: 1 . A method for receiving and processing a wireless signal, the method comprising: receiving an encoded wireless signal at an antenna; decoding at least a first portion of the wireless signal at a first voltage range above a threshold level to generate a first component of the encoded wireless signal; attenuating at least a second portion of the wireless signal and generating an attenuated signal having a second voltage below the threshold level; decoding the attenuated signal to generate a second component of the encoded wireless signal; and switching between a standby mode and an operating mode based on the second component of the encoded wireless signal. 2 . The method according to claim 1 wherein a symmetrical attenuation unit attenuates the at least second portion of the wireless signal and generates the attenuated signal. 3 . The method according to claim 1 wherein the attenuation of the at least second portion of the wireless signal is performed in accordance with a plurality of voltage reduction steps within a hardware voltage divider in an attenuation unit. 4 . The method according to claim 3 wherein the attenuation of the at least second portion of the wireless signal is differential. 5 . The method according to claim 11 further comprising the step of rectifying the attenuated signal. 6 . The method according to claim 11 further comprising the step of tapping the at least second portion of the wireless signal between capacitors within the antenna. 7 . An electronic circuit comprising: an interface that receives a signal and outputs an encoded signal; a plurality of decoders coupled to receive the encoded signal, the plurality of decoders decodes the encoded signal in stages wherein at least a first portion of the encoded signal is decoded by a first stage of the plurality of decoders and a second portion of the encoded signal is decoded by a second stage of the plurality of decoders, the first and second stages of the plurality of decoders operating at different voltage levels; and an attenuator coupled to the interface, the attenuator adjusts a voltage level on one or more portions of the encoded signal relative to a voltage range. 8 . The electronic circuit of claim 7 wherein the attenuator comprises a voltage divider that adjusts the voltage level on the one or more portions of the encoded signal. 9 . The electronic circuit of claim 8 wherein the voltage divider is symmetrical relative to ground. 10 . The electronic circuit of claim 8 wherein the voltage divider operates in a differential mode. 11 . The electronic circuit of claim 7 wherein the interface receives an encoded wireless signal. 12 . The electronic circuit of claim 7 further comprising a voltage sensor coupled to the interface, the voltage sensor detects a voltage level on the encoded signal. 13 . The electronic circuit of claim 7 wherein the electronic circuit is located within an RFID chip. 14 . The electronic circuit of claim 7 further comprising wake-up circuitry that activates the electronic circuit in response to the signal received at the interface being in a defined voltage range. 15 . The electronic circuit of claim 7 further comprising wake-up circuitry that activates the electronic circuit in response to the signal having a specific bit sequence identified as a wake-up command. 16 . An electronic circuit comprising: an interface that receives an encoded signal; a first decoder coupled to receive at least a first portion of the encoded signal, the first decoder decodes the first portion of the encoded signal; a second decoder coupled to receive at least a second portion of the encoded signal, the second decoder decodes the second portion of the encoded signal; and a rectifying element coupled to receive the decoded second portion of the encoded signal, the rectifying element generates a rectified signal. 17 . The electronic circuit of claim 16 wherein the rectifying element is a half-wave rectifier. 18 . The electronic circuit of claim 16 wherein the rectifying element is a full-wave rectifier. 19 . The electronic circuit of claim 16 further comprising a controller coupled to the first and second decoders, the controller defines at least one operating parameter for the first and second decoders. 20 . The electronic circuit of claim 19 wherein the controller defines a first voltage range for the first decoder and a second voltage range for the second decoder.

Assignees

Inventors

Classifications

  • G06K7/0008Primary

    General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer · CPC title

  • in amplifiers having discharge tubes · CPC title

  • the arrangement including means to regulate power transfer to the integrated circuit · CPC title

  • the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card · CPC title

  • H04B7/0871Primary

    using different reception schemes, at least one of them being a diversity reception scheme · CPC title

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What does patent US2016006497A1 cover?
An electronic circuit arrangement for receiving low-frequency electromagnetic waves is proposed, having an inductor (L) acting as an antenna for generating a received signal, having a first receiver ( 2 ), connected to the inductor (L), for decoding a first component of the received signal and having a second receiver ( 3 ), connected to the inductor (L), for decoding a second component of the …
Who is the assignee on this patent?
Maxim Integrated Products
What technology area does this patent fall under?
Primary CPC classification G06K7/0008. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jan 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).