Digitally controlled delay-locked loop reference generator

Patent metadata

Field	Value
Publication number	US-2016006444-A1
Application number	US-201414486694-A
Country	US
Kind code	A1
Filing date	Sep 15, 2014
Priority date	Jul 4, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

A system and method for a digitally controlled delay-locked loop reference generator is disclosed.

First claim

1 . A system for generating a timing delay signal, comprising:
a phase error detector for determining the phase error between a first periodic signal and a second periodic signal; a counter for receiving one or more outputs from the phase error detector and generating a digital signal; a controller for receiving the digital signal and generating a signal to drive a current control delay loop, the current control delay loop generating the second periodic signal and the timing delay signal.

2 . The system of claim 1 , further comprising:
a reference clock for generating the first periodic signal;

3 . The system of claim 1 , further comprising:
a frequency divider for generating the first periodic signal in response to a third periodic signal.

4 . The system of claim 3 , further comprising:
a reference clock for generating the third periodic signal.

5 . The system of claim 4 , wherein the reference clock comprises a crystal oscillator.

6 . The system of claim 3 , wherein the frequency of the third periodic signal is an integer multiple of the frequency of the first periodic signal.

7 . The system of claim 1 , wherein the digital signal comprises at least four bits.

8 . The system of claim 7 , wherein the digital signal comprises at least eight bits.

9 . The system of claim 1 , wherein the counter increments the digital signal when one output is asserted and decrements the digital signal when another output is asserted.

10 . The system of claim 2 , wherein the counter increments the digital signal when one output is asserted and decrements the digital signal when another output is asserted.

11 . The system of claim 3 , wherein the counter increments the digital signal when one output is asserted and decrements the digital signal when another output is asserted.

12 . The system of claim 4 , wherein the counter increments the digital signal when one output is asserted and decrements the digital signal when another output is asserted.

13 . The system of claim 5 , wherein the counter increments the digital signal when one output is asserted and decrements the digital signal when another output is asserted.

14 . The system of claim 1 , wherein the timing delay signal is asserted after a time interval has elapsed after the beginning of a cycle of the first periodic signal, wherein the time interval is a predetermined portion of the period of the first periodic signal.

15 . The system of claim 2 , wherein the timing delay signal is asserted after a time interval has elapsed after the beginning of a cycle of the first periodic signal, wherein the time interval is a predetermined portion of the period of the first periodic signal.

16 . The system of claim 3 , wherein the timing delay signal is asserted after a time interval has elapsed after the beginning of a cycle of the first periodic signal, wherein the time interval is a predetermined portion of the period of the first periodic signal.

17 . The system of claim 4 , wherein the timing delay signal is asserted after a time interval has elapsed after the beginning of a cycle of the first periodic signal, wherein the time interval is a predetermined portion of the period of the first periodic signal.

18 . A system for generating a timing delay signal, comprising:
a reference clock for generating a first periodic signal; a frequency divider for generating a second periodic signal with a frequency that is a predetermined fraction of the frequency of the first periodic signal; phase error detector for determining the phase error between the second periodic signal and a third periodic signal; a counter for receiving one or more outputs from the phase error detector and generating a digital signal; and a controller for receiving the digital signal and generating a signal to drive a current control delay loop, the current control delay loop generating the third periodic signal and the timing delay signal.

19 . The system of claim 18 , wherein the timing delay signal is asserted after a time interval has elapsed after the beginning of a cycle of the first periodic signal, wherein the time interval is a predetermined portion of the period of the first periodic signal.

20 . The system of claim 18 , wherein the timing delay signal is asserted after a time interval has elapsed after the beginning of a cycle of the second periodic signal, wherein the time interval is a predetermined portion of the period of the second periodic signal.

Assignees

• Silicon Storage Tech Inc

Inventors

• Zhou Yao
• Cao Yuou
• Qian Xiaozhou
• Bai Ning
• Xu Xinyan

Classifications

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title

• H03L7/0816

  the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title

• H03L7/083

  the reference signal being additionally directly applied to the generator · CPC title