Solid-state image pickup device, method of manufacturing thereof, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-2016005784-A1
Application number	US-201514855775-A
Country	US
Kind code	A1
Filing date	Sep 16, 2015
Priority date	Mar 24, 2010
Publication date	Jan 7, 2016
Grant date	—

Abstract

Provided is a solid-state image pickup device including: a plurality of pixels, each of which includes a photoelectric conversion portion and a pixel transistor formed in a front surface side of a substrate, wherein a rear surface side of the substrate is set as a light receiving plane of the photoelectric conversion portion; and an element, which becomes a passive element or an active element, which is disposed in the front surface side of the substrate so as to be superimposed on the photoelectric conversion portion.

First claim

What is claimed is:

1 . A solid-state image pickup device comprising:
a plurality of pixels, at least one pixel including a photoelectric conversion portion and a pixel transistor embedded within a semiconductor substrate at a front surface side of the semiconductor substrate, wherein a rear surface side of the semiconductor substrate corresponds to a light receiving plane of the photoelectric conversion portion; and an active or passive pixel element disposed within the front surface side of the semiconductor substrate so as to be superimposed on the photoelectric conversion portion.

2 . The solid-state image pickup device according to claim 1 , wherein the passive pixel element is a capacitance element comprising a wire line and an interlayer insulating film disposed within the front surface side of the semiconductor substrate.

3 . The solid-state image pickup device according to claim 2 , wherein the capacitance element is configured to store charges transferred from the photoelectric conversion portion.

4 . The solid-state image pickup device according to claim 2 , wherein the capacitance element is an analog/digital conversion circuit.

5 . The solid-state image pickup device according to claim 1 , wherein the passive pixel element is an inductance element and/or a resistance element.

6 . The solid-state image pickup device according to claim 1 , wherein the active pixel element is a transistor element.

7 . The solid-state image pickup device according to claim 6 , wherein the transistor element is another pixel transistor.

8 . The solid-state image pickup device according to claim 1 , further comprising:
a first semiconductor chip including an image pickup area comprising the plurality of the pixels arranged in a two-dimensional array shape; and a second semiconductor chip including at least a logic circuit, wherein the first and second semiconductor chips are laminated together.

9 . A method of manufacturing a solid-state image pickup device, comprising the steps of:
forming a plurality of pixels in a semiconductor substrate, at least one pixel including a photoelectric conversion portion and a pixel transistor embedded within the semiconductor substrate at a front surface side of the semiconductor substrate, wherein a rear surface side of the semiconductor substrate corresponds to a light receiving plane of the photoelectric conversion portion; and forming an active or passive pixel element disposed within the front surface side of the semiconductor substrate so as to be superimposed on the photoelectric conversion portion.

10 . The method according to claim 9 , further comprising, after the step of forming the plurality of pixels, the step of forming wire lines of a plurality of layers through interlayer insulating films disposed within the front surface of the semiconductor substrate and thereby forming the passive pixel circuit element.

11 . The method according to claim 10 , wherein the passive pixel element is a capacitance element.

12 . The method according to claim 10 , wherein the passive pixel element is an inductance element and/or a resistance element.

13 . The method according to claim 9 , further comprising, after the step of forming the plurality of pixels, the steps of forming the active pixel element on the front surface of the semiconductor substrate and forming wire lines of a plurality of layers through interlayer insulating films.

14 . The method according to claim 13 , wherein the active pixel element is another transistor element.

15 . An electronic apparatus comprising:
a solid-state image pickup device; an optical system configured to guide incident light to a photodiode of the solid-state image pickup device; and a signal processing circuit configured to perform a process on an output signal of the solid-state image pickup device, wherein the solid-state image pickup device comprises:
a plurality of pixels, at least one pixel including a photoelectric conversion portion and a pixel transistor embedded within a semiconductor substrate at a front surface side of the semiconductor substrate, wherein a rear surface side of the semiconductor substrate corresponds to a light receiving plane of the photoelectric conversion portion; and
an active or passive pixel element disposed within the front surface side of the semiconductor substrate so as to be superimposed on the photoelectric conversion portion.

16 . The electronic apparatus according to claim 15 , wherein the passive pixel element is a capacitance element comprising a wire line and an interlayer insulating film disposed within the front surface side of the semiconductor substrate.

17 . The electronic apparatus according to claim 16 , wherein the capacitance element is configured to store charges transferred from the photoelectric conversion portion.

18 . The electronic apparatus according to claim 16 , wherein the capacitance element is an analog/digital conversion circuit.

19 . The electronic apparatus according to claim 15 , wherein the passive pixel element is an inductance element and/or a resistance element.

20 . The electronic apparatus according to claim 15 , wherein the active pixel element is a transistor element.

21 . The electronic apparatus according to claim 20 , wherein the transistor element is another pixel transistor.

22 . The electronic apparatus according to claim 15 , further comprising:
a first semiconductor chip including an image pickup area comprising the plurality of the pixels arranged in a two-dimensional array shape; and a second semiconductor chip including at least a logic circuit, wherein the first and second semiconductor chips are laminated together.

Assignees

• Sony Corp

Inventors

• Kiyota Yukihiro
• Mabuchi Keiji

Classifications

• H04N25/70

  SSIS architectures; Circuits associated therewith · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H10F39/8063

  Microlenses · CPC title

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H10F39/1825

  Multicolour image sensors having stacked structure, e.g. NPN, NPNPN or multiple quantum well [MQW] structures · CPC title