Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016005745-A1
Application number	US-201514855754-A
Country	US
Kind code	A1
Filing date	Sep 16, 2015
Priority date	Jun 3, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

A semiconductor device includes a substrate having a cell region, wherein a contact region, page buffer regions, and a scribe lane region are defined around the cell region; a cell structure located in the cell region, including first conductive layers and first insulating layers which are alternately stacked, and having a non-stepped shape; a contact structure located in the contact region, including second conductive layers and second insulating layers which are alternately stacked, and having a stepped shape; a first dummy structure located in the page buffer region, including first sacrificial layers and third insulating layers which are alternately stacked, and having the non-stepped shape; and a second dummy structure located in the scribe lane region, including second sacrificial layers and fourth insulating layers which are alternately stacked, and having the stepped shape.

First claim

1 - 14 . (canceled)

15 . A method of manufacturing a semiconductor device, comprising:
forming a stacked structure in which first material layers and second material layers are alternately stacked on a substrate having a cell region, wherein contact regions, a page buffer region, and a scribe lane region are disposed around the cell region; and patterning the stacked structure, and forming a cell structure having a non-stepped shape located in the cell region, a contact structure having a stepped shape located in the contact region, a first dummy structure having the non-stepped shape located in the page buffer region, and a second dummy structure having the stepped shape located in the scribe lane region.

16 . The method of claim 15 , wherein the patterning of the stacked structure comprises:
forming a mask pattern on the stacked structure; and etching the stacked structure a number of times while reducing the mask pattern so that the mask pattern covers the cell region and the page buffer region, and the contact region and the scribe lane region are gradually exposed.

17 . The method of claim 15 , wherein the contact regions contact a first side and a second side of the cell region which face each other, and the scribe lane region and the page buffer region contact a third side and a fourth side of the cell region which face each other.

18 . The method claim 15 , further comprising:
forming a first trench located between the cell structure and the first dummy structure; and forming a first blocking insulator in the first trench.

19 . The method of claim 18 , further comprising:
forming a second trench penetrating the cell structure, after forming the first blocking insulator; selectively removing the first material layers included in the cell structure through the second trench; and forming conductive layers in areas in which the first material layers are removed.

20 . The method of claim 15 , further comprising:
forming a third trench located between the cell structure and the second dummy structure; and forming a second blocking insulator in the third trench.

Assignees

• Sk Hynix Inc

Inventors

• Kim Won Ki
• Kim Jong Man

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H01L27/115 Primary

  Electricity · mapped topic

• H01L21/28

  Electricity · mapped topic