Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2016005665-A1
Application number	US-201514738858-A
Country	US
Kind code	A1
Filing date	Jun 13, 2015
Priority date	Jul 7, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

Reading reliability of a code formed in a semiconductor device is improved.
A manufacturing method of semiconductor devices according to one embodiment includes a step of forming a sealing body MR in a plurality of device regions DVP with a code (first identification information) MK 3 being formed outside the device regions DVP of a wiring substrate. Also, the manufacturing method of semiconductor devices according to one embodiment includes a step of, after forming the sealing body MR, reading the code MK 3 and affixing another code (second identification information) to the sealing body MR. Further, before the step of forming the sealing body MR, a dam part DM is formed between a marking region MKR in which the code MK 3 is formed and the device regions DVP.

First claim

What is claimed is:

1 . A method of manufacturing semiconductor devices, comprising the steps of:
(a) providing a base material having a first surface, a plurality of device regions formed in the first surface, a plurality of semiconductor chips mounted in the plurality of device regions, respectively, a frame region provided in the first surface and outside the plurality of device regions, a marking region provided in part of the frame region, and first identification information affixed to the marking region, wherein the first surface has a first side and a second side opposed to the first side; wherein the frame region has a first region located between the device regions and the first side and a second region other than the frame region; and wherein the marking region is provided in the second region; (b) after the step (a), sealing the plurality of semiconductor chips with resin and forming a sealing body by clamping the base material using a first metal mold and a second metal mold such that the plurality of semiconductor chips are located inside a cavity provided in the first metal mold and supplying resin into the cavity from the side of the first side of the base material; (c) after the step (b), reading the first identification information; and (d) after the step (b), newly affixing a second identification information to the sealing body, wherein, before the step (b), a dam part is formed between the marking region and the plurality of device regions of the frame region.

2 . The method of manufacturing semiconductor devices according to claim 1 ,
wherein the first metal mold has a gate part in communication with the cavity and a vent part arranged on the opposite side of the gate part through the cavity and in communication with the cavity; wherein, in the step (b), the resin is supplied from the gate part arranged on the side of the first side of the base material and a gas inside the cavity is discharged from the vent part arranged on the side of the second side of the base material; and wherein the second region of the frame region is located between the second side and the plurality of device regions.

3 . The method of manufacturing semiconductor devices according to claim 1 ,
wherein the base material is a wiring substrate having an insulating layer, a plurality of wires formed in the insulating layer, and a plurality of terminals formed in the insulating layer.

4 . The method of manufacturing semiconductor devices according to claim 1 ,
wherein the base material is a wiring substrate having a first insulating film formed on the first surface side; wherein there are formed, on the side of the first side of the base material, a plurality of gate patterns which are metal patterns exposed from the first insulating film and are arranged at a position overlapping a supply port of the resin in the step (b); wherein, on the side of the second side of the base material, there are formed a plurality of vent patterns which are trench patterns formed in the first insulating film, arranged at a position overlapping an outlet of a gas inside the cavity in the step (b); and wherein, in an extending direction of the first side and the second side of the base material, a width of each of the plurality of gate patterns is greater than a width of each of the plurality of vent patterns.

5 . The method of manufacturing semiconductor devices according to claim 4 ,
wherein the second region of the frame region is located between the second side and the plurality of device regions.

6 . The method of manufacturing semiconductor devices according to claim 5 ,
wherein the vent patterns are formed in the second region; and wherein, the marking region is formed between adjacent vent patterns of the plurality of vent patterns.

7 . The method of manufacturing semiconductor devices according to claim 1 ,
wherein the semiconductor chip is electrically coupled with a plurality of terminals formed in the base material via a plurality of wires, and wherein, in the step (b), the sealing body is formed by sealing the semiconductor chips and the wires in the cavity with the resin.

8 . The method of manufacturing semiconductor devices according to claim 1 ,
wherein the dam part is a trench pattern formed in the first surface of the base material.

9 . The method of manufacturing semiconductor devices according to claim 1 ,
wherein the base material is a wiring substrate having an insulating layer, a plurality of wirings formed in the insulating layer, a plurality of terminals formed in the insulating layer, and a first insulating film covering the wirings on the side of the first surface, and wherein the dam part is a trench pattern formed by removing the first insulating film.

10 . The method of manufacturing semiconductor devices according to claim 1 ,
wherein the first surface of the base material is quadrangular; wherein the dam part has a first portion extending along a first portion extending along a first direction in which a side where the marking region is formed extends, a second portion extending along a second direction orthogonal to the first direction, and a third portion opposed to the second portion and extending along the second direction, and wherein one end of each of the second and third portion is connected to the first portion and the other end extends to the side where the marking region is formed.

11 . The method of manufacturing semiconductor devices according to claim 10 ,
wherein each of the first, second, and third portions extends in a rectilinear manner.

12 . The method of manufacturing semiconductor devices according to claim 10 ,
wherein one or both of the second and third portions extend (s) toward the second direction in a meandering manner.

13 . The method of manufacturing semiconductor devices according to claim 1 ,
wherein, in the step (b), in a state where the base material is arranged between the first metal mold and the second metal mold such that the device regions are positioned inside the one cavity, the sealing body is formed by collectively sealing the device regions.

Assignees

• Renesas Electronics Corp

Inventors

• Suzuki Masakatsu
• Saito Koji
• Otake Mamoru

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/656

  Fan-in layouts · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/073

  of die-attach connectors · CPC title