Determining soft data
US-2015348619-A1 · Dec 3, 2015 · US
Memory devices and programming memory arrays thereof
US2016005474A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016005474-A1 |
| Application number | US-201514857475-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 17, 2015 |
| Priority date | Jul 30, 2012 |
| Publication date | Jan 7, 2016 |
| Grant date | — |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.
First claim
Opening claim text (preview).
What is claimed is: 1 . A memory device, comprising: a memory array; and control logic; wherein the control logic is configured to decrease a difference of a voltage applied to a first select gate of the memory array minus a voltage applied to a source of the memory array coupled to the first select gate while the first select gate is off; wherein the control logic is configured to decrease a difference of a voltage applied to a second select gate of the memory array minus…
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Physics · mapped topic
- G11C16/10Primary
Physics · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2016005474A1 cover?
- An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that i…
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C16/10. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Jan 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).