Data storage device

Patent metadata

Field	Value
Publication number	US-2016005444-A1
Application number	US-201414512126-A
Country	US
Kind code	A1
Filing date	Oct 10, 2014
Priority date	Jul 2, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

A data storage device includes a first memory device suitable for performing an internal operation in response to a first internal operation command; and a state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation.

First claim

What is claimed is:

1 . A data storage device comprising:
a first memory device suitable for performing an internal operation in response to a first internal operation command; and a state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation.

2 . The data storage device according to claim 1 , wherein the state checking block sets an initial standby time during the initial mode based on an expected performance time of the internal operation, and transmits an initial state read command to the first memory device when the initial standby time passes.

3 . The data storage device according to claim 2 ,
wherein the first memory device outputs initial response data in response to the initial state read command, and wherein the state checking block determines whether the internal operation is completed based on the initial response data, and ends the state read operation or enters the repeat mode according to a determination result.

4 . The data storage device according to claim 3 , wherein the state checking block sets a repeat standby time during the repeat mode based on the expected performance time of the internal operation when it is determined that the internal operation is not completed, and transmits a repeat state read command to the first memory device when the repeat standby time passes.

5 . The data storage device according to claim 4 ,
wherein the first memory device outputs repeat response data in response to the repeat state read command, and wherein the state checking block determines whether the internal operation is completed based on the repeat response data, and ends the state read operation or retains the repeat mode according to a determination result.

6 . The data storage device according to claim 5 , wherein the state checking block repeatedly transmits the repeat state read command each time the repeat standby time passes when retaining the repeat mode.

7 . The data storage device according to claim 1 , wherein the state checking block ends the state read operation when the state read operation is performed for a preset time or when the number of transmission times of the state read command reaches a preset number of times during the repeat mode.

8 . The data storage device according to claim 1 , further comprising:
a processor configured to transmit the first internal operation command to the first memory device, and transmit information on a type of the internal operation to the state checking block.

9 . The data storage device according to claim 8 , wherein the state checking block outputs a permission request signal to the processor and receives a permission signal from the processor before transmitting the state read command.

10 . The data storage device according to claim 1 , wherein the state checking block reports to the processor whether a result of the internal operation is a success or a failure or if a time-out occurs in the first memory device when ending the state read operation.

11 . The data storage device according to claim 1 , further comprising a second memory device,
wherein the processor transmits a second internal operation command to the second memory device after transmitting the first internal operation command, and wherein the state checking block performs state checking operations for the respective first and second memory devices.

12 . The data storage device according to claim 11 , wherein the state checking block transmits the state read command to the second memory device when it is determined that the internal operation of the first memory device is completed.

13 . The data storage device according to claim 11 , wherein the state checking block transmits the state read command to the second memory device regardless of whether the internal operation of the first memory device is completed.

14 . A data storage device comprising:
a memory device suitable for performing an internal operation in response to an internal operation command; and a state checking block suitable for determining whether the internal operation is completed, wherein the state checking block comprises: a sequencer suitable for setting a standby time based on an internal operation information, and checking passage of the standby time; a pattern generation unit suitable for generating a state read command; and a main control unit suitable for transmitting the state read command to the memory device based on timing report of the sequencer due to the passage of the standby time.

15 . The data storage device according to claim 14 , wherein the internal operation information comprises information on a type of the internal operation and an address of the memory device.

16 . The data storage device according to claim 14 ,
wherein the memory device outputs response data in response to the state read command, and wherein the sequencer determines whether the Internal operation is completed based on the response data.

17 . The data storage device according to claim 16 , wherein the sequencer repeatedly sets a repeat standby time based on the internal operation information and transmits the state read command each time the repeat standby time passes until it is determined that the internal operation is completed.

18 . The data storage device according to claim 17 , wherein the sequencer sets the repeat standby time to be shorter than the initial standby time.

19 . The data storage device according to claim 14 , further comprising a processor configured to transmit the internal operation command to the memory device, and transmit the internal operation information to the state checking block.

20 . The data storage device according to claim 19 , wherein the main control unit outputs a permission request signal to the processor, and receives a permission signal from the processor before transmitting the state read command.

Assignees

• Sk Hynix Inc

Inventors

• Chun Dong Yeob
• An Joong Hyun
• Kim Kwang Hyun

Classifications

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G11C2207/2227

  Standby or low power modes · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G11C16/32

  Timing circuits · CPC title