Display driving circuit and output buffer circuit thereof

Patent metadata

Field	Value
Publication number	US-2016005374-A1
Application number	US-201514792811-A
Country	US
Kind code	A1
Filing date	Jul 7, 2015
Priority date	Jul 7, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

Provided are an output buffer circuit capable of outputting a pair of output signals having different polarities and a display driving circuit including the same. The output buffer circuit includes output buffers which output a positive output signal and a negative output signal in response to a pair of input signals having different polarities. As the output buffers are driven while sharing a common voltage, the output buffer circuit satisfies a low-power specification, and has a stable electrical characteristic.

First claim

What is claimed is:

1 . An output buffer circuit of a display driving circuit, comprising:
a first output buffer configured to output a first output signal to a display panel using a first voltage and a common voltage lower than the first voltage in response to a first input signal; and a second output buffer configured to output a second output signal to the display panel using the common voltage and a second voltage lower than the common voltage in response to a second input signal, wherein the first output buffer comprises one or more first NMOS transistors driven by the common voltage in order to receive the first input signal or output the first output signal, the second output buffer comprises one or more second NMOS transistors driven by the second voltage in order to receive the second input signal or output the second output signal, and the first NMOS transistor is electrically isolated so as to be prevented from being shorted to the second NMOS transistor via a substrate.

2 . The output buffer circuit of claim 1 , wherein the first input signal and the second input signal have different polarities.

3 . The output buffer circuit of claim 1 , wherein the first NMOS transistor is configured to receive the common voltage as a body voltage.

4 . The output buffer circuit of claim 1 , wherein the first NMOS transistor is formed in a P-well formed within an N-type isolation well, and the first NMOS transistor and the substrate are electrically isolated from each other by the N-type isolation well.

5 . The output buffer circuit of claim 4 , wherein the first voltage is biased to the N-type isolation well.

6 . The output buffer circuit of claim 1 , wherein the first voltage comprises a driving voltage, the second voltage comprises a ground voltage, and the common voltage is set to ½ level of the driving voltage.

7 . The output buffer circuit of claim 1 , wherein the common voltage is set to a ground level.

8 . A display driving circuit comprising:
a first output buffer configured to output a first output signal to a display panel using a first voltage and a common voltage lower than the first voltage in response to a first input signal; a second output buffer configured to output a second output signal to the display panel using the common voltage and a second voltage lower than the common voltage in response to a second input signal; and a switching circuit configured to output the first and second output signals to first and second output terminals, wherein the switching circuit is implemented with a high-voltage transistor, and the first and second output buffers are implemented with a low-voltage transistor which is driven by a driving voltage lower than the high-voltage transistor and has a lower withstanding voltage than the high-voltage transistor.

9 . The display driving circuit of claim 8 , wherein the first output buffer comprises one or more first NMOS transistors which are driven by the common voltage in order to receive the first input signal or output the first output signal and correspond to the low-voltage transistor,
the second output buffer comprises one or more second NMOS transistors which are driven by the second voltage in order to receive the second input signal or output the second output signal and correspond to the low-voltage transistor, and the first NMOS transistor is electrically isolated so as to be prevented from being shorted to the second NMOS transistor via the substrate.

10 . The display driving circuit of claim 9 , wherein the first NMOS transistor is formed in a P-well formed within an N-type isolation well, and the first NMOS transistor and the substrate are electrically isolated from each other by the N-type isolation well.

11 . The display driving circuit of claim 10 , wherein the first voltage is biased to the N-type isolation well.

12 . The display driving circuit of claim 1 , wherein the first input signal and the second input signal have different polarities.

Assignees

• Silicon Works Co Ltd

Inventors

• Kim Young Bok
• Kim Young Tae
• Jeon Hyun Kyu
• Na Joon Ho

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G3/3696 Primary

  Generation of voltages supplied to electrode drivers · CPC title

• G09G3/3614

  Control of polarity reversal in general · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2330/023

  using energy recovery or conservation · CPC title