Microcontroller with multiple power modes

Patent metadata

Field	Value
Publication number	US-2016004292-A1
Application number	US-201414321838-A
Country	US
Kind code	A1
Filing date	Jul 2, 2014
Priority date	Jul 2, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.

First claim

1 . An integrated circuit (IC) operable in a high power mode and a low power unit (LPU) run mode, comprising:
a primary domain including:
a first set of circuits;
a first set of cores having at least one core that operates when the IC is in the high power mode and is powered off when the IC is in the LPU run mode; and
a first cross-bar bus, connected between the first set of cores and the first set of circuits, that configures a connection between the first set of cores and the first set of circuits; and
a LPU domain including:
second and third sets of circuits;
a second set of cores having at least one core that operates when the integrated circuit is in the high power and LPU run modes; and
a switching module, connected to the second set of cores, the first cross-bar bus, and the second and third sets of circuits, that connects the second set of cores to at least one of the first, second and third sets of circuits by way of the first cross-bar bus when the IC is in the high power mode, and connects the second set of cores directly to at least one of the second and third sets of circuits when the IC is in the LPU run mode.

2 . The IC of claim 1 , wherein the switching module further connects the first set of cores to the at least one of the second and third sets of circuits by way of the first cross-bar bus when the IC is in the high power mode, and disables a connection between the second set of cores and at least one of the first, second and third sets of circuits by way of the first cross-bar bus when the IC is in the LPU run mode.

3 . The IC of claim 2 , wherein the switching module comprises:
a first switcher, connected to the second set of cores and the first cross-bar bus, that connects the second set of cores to the first cross-bar bus when the IC is in the high power mode and disconnects the second set of cores from the first cross-bar bus when the IC is in the LPU run mode; a second cross-bar bus, connected to the first switcher, wherein the first switcher disconnects the second set of cores from the second cross-bar bus when the IC is in the high power mode and connects the second set of cores to the second cross-bar bus when the IC is in the LPU run mode; and a second switcher, connected to the first and second cross-bar buses and the second and third sets of circuits, that connects the first set of cores to at least one of the second and third sets of circuits by way of the first cross-bar bus and the second set of cores to the at least one of the second and third sets of circuits by way of the first switcher and the first cross-bar bus when the IC is in the high power mode, and connects the second set of cores to the at least one of the second and third sets of circuits by way of the first switcher and the second cross-bar bus when the IC is in the LPU run mode.

4 . The IC of claim 3 , wherein the IC also is operable in a LPU sleep mode, a LPU stop mode, and a LPU standby mode, and wherein the primary domain is powered on when the IC is in the high power mode and is powered off when the IC is in any one of the LPU run mode, LPU sleep mode, LPU stop mode and LPU standby mode.

5 . The IC of claim 4 , further comprising:
a primary clock generator module, connected to the primary domain, that generates and provides a first clock signal to the primary domain when the IC is in the high power mode and is powered off when the IC is in any one of the LPU run, LPU sleep, LPU stop and LPU standby modes; and a LPU clock generator module, connected between the LPU domain and the primary clock generator module, that generates and provides a second clock signal to the LPU domain when the IC is in the LPU run mode and is deactivated when the IC is in the high power mode, wherein the primary clock generator module further provides the first clock signal to the LPU domain by way of the LPU clock generator module when the IC is in the high power mode.

6 . The IC of claim 5 , wherein the second clock signal provided to the second set of cores is gated and the LPU clock generator module provides the second clock signal to the second and third sets of circuits when the IC is in the LPU sleep mode, and wherein the second clock signal provided to the LPU domain is gated when the IC is in the LPU stop mode, and wherein the second set of cores and the second set of circuits are powered off and the LPU clock generator module provides the second clock signal to the third set of circuits when the IC is in the LPU standby mode.

7 . The IC of claim 6 , further comprising:
a primary mode controller, connected to the primary domain and the primary clock generator module, that generates and provides a first set of control signals to the primary domain and the primary clock generator module when the IC is in the high power mode and is powered off when the IC is in any one of the LPU run, LPU sleep, LPU stop and LPU standby modes; and a LPU mode controller, connected to the LPU domain, the LPU clock generator module and the primary mode controller, that generates and provides a second set of control signals to the LPU domain and the LPU clock generator module when the IC is in any one of the LPU run, LPU sleep, LPU stop and LPU standby modes, and is deactivated when the IC is in the high power mode, and wherein the primary mode controller further provides the first set of control signals to the LPU domain by way of the LPU mode controller when the IC is in the high power mode.

8 . The IC of claim 7 , wherein the first set of control signals configures the primary clock generator module, and the primary and LPU domains when the IC is in the high power mode, and wherein the second set of control signals configures the LPU clock generator module and the LPU domain when the IC is in any one of the LPU run, LPU sleep, LPU stop and LPU standby modes.

9 . The IC of claim 1 , wherein the second set of circuits includes at least one of a controller area network (CAN) and a local interconnect network (LIN).

10 . A microcontroller operable in high power and low power unit (LPU) run modes, comprising:
first, second and third sets of circuits; first and second sets of cores each having at least one core, wherein the first set of cores operates when the microcontroller is in the high power mode and is powered off when the integrated circuit is in the LPU run mode, and wherein the second set of cores operates when the microcontroller is in the high power and LPU run modes; a first cross-bar bus, connected between the first set of cores and the first set of circuits, that configures a connection between the first set of cores and the first set of circuits; a first switcher, connected to the second set of cores and the first cross-bar bus, that connects the second set of cores to the first set of circuits by way of the first cross-bar bus when the microcontroller is in the high power mode and disconnects the second set of cores from the first cross-bar bus when the microcontroller is in the LPU run mode; a second cross-bar bus, connected to the first switcher, wherein the first switcher disconnects the second set of cores from the second cross-bar bus when the microcontroller is in the high power mode and connects the second set of cores to the second cross-bar bus when the microcontroller is in the LPU run mode; and a second switcher, connected to the first and second cross-bar buses and the second and third sets of circuits, that connects the second set of cores to at least one of the second and third sets of circuits by way of the first switcher and the first cross-bar bus and the first set of cores to the at least one of the second and third sets of circuits by way of the first cross-bar bus when the microcontroller is in the high po

Assignees

• Sharda Garima
• Culshaw Carl
• Devine Alan
• Pathak Akshay K
• Robertson Alistair P
• Freescale Semiconductor Inc

Inventors

• Sharda Garima
• Culshaw Carl
• Devine Alan
• Pathak Akshay K
• Robertson Alistair P

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title