Wiring board and method for manufacturing the same

US2015382471A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2015382471-A1
Application numberUS-201514846084-A
CountryUS
Kind codeA1
Filing dateSep 4, 2015
Priority dateJan 12, 2012
Publication dateDec 31, 2015
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A wiring board includes a substrate which has multiple opening portions and one or more boundary portions separating the opening portions, multiple electronic devices positioned in the opening portions of the substrate, respectively, a conductive pattern formed on a surface of the boundary portion, and an insulation layer formed on the substrate and the conductive pattern on the boundary portion of the substrate such that the insulation layer covers the electronic devices in the opening portions of the substrate. The boundary portion has a width which is in a range of approximately 0.05 to approximately 2.0 mm.

First claim

Opening claim text (preview).

What is claimed is: 1 . A wiring board, comprising: a substrate which has a plurality of opening portions and at least one boundary portion separating the opening portions; a plurality of electronic devices positioned in the plurality of opening portions of the substrate, respectively; a conductive pattern formed on a surface of the boundary portion; and an insulation layer formed on the substrate and the conductive pattern on the boundary portion of the substrate such that the insulation layer covers the plurality of electronic devices in the plurality of opening portions of the substrate, wherein the boundary portion has a width which is in a range of approximately 0.05 to approximately 2.0 mm. 2 . The wiring board according to claim 1 , further comprising an opposing conductive pattern formed on an opposite surface of the boundary portion with respect to the conductive pattern on the surface of the boundary portion. 3 . The wiring board according to claim 2 , wherein the boundary portion has a width which is in a range of approximately 0.2 to approximately 2.0 mm. 4 . The wiring board according to claim 1 , wherein the boundary portion has a width which is in a range of approximately 0.2 to approximately 2.0 mm. 5 . The wiring board according to claim 1 , further comprising a via conductor formed in the insulation layer such that the via conductor is positioned to be connected to an electrode of one of the electronic components. 6 . The wiring board according to claim 1 , wherein the conductive pattern on the boundary portion is electrically connected to one of a power-source terminal and a ground terminal of each of the electronic devices. 7 . The wiring board according to claim 4 , wherein the conductive pattern on the boundary portion is electrically connected to one of a power-source terminal and a ground terminal of each of the electronic devices. 8 . The wiring board according to claim 1 , further comprising a first via conductor formed in the insulation layer such that the first via conductor is electrically connected to the conductive pattern on the boundary portion. 9 . The wiring board according to claim 4 , further comprising a first via conductor formed in the insulation layer such that the first via conductor is electrically connected to the conductive pattern on the boundary portion. 10 . The wiring board according to claim 1 , further comprising a first via conductor formed in the insulation layer. 11 . The wiring board according to claim 1 , wherein the conductive pattern on the boundary portion has substantially a constant width. 12 . The wiring board according to claim 1 , wherein the boundary portion of the substrate has a substantially cruciform planar shape such that the boundary portion forms the plurality of opening portions consisting of four opening portions, and the conductive pattern on the boundary portion is a substantially cruciform conductive pattern formed on the boundary portion. 13 . The wiring board according to claim 1 , wherein the boundary portion of the substrate has a substantially T-shaped planar shape such that the boundary portion forms the plurality of opening portions consisting of three opening portions, and the conductive pattern on the boundary portion is a substantially T-shaped conductive pattern formed on the boundary portion. 14 . The wiring board according to claim 1 , wherein the plurality of electronic devices includes a first electronic device and a second electronic device, each of the first electronic device and the second electronic device has a first side electrode on a first side surface and a second side electrode on a second side surface on an opposite side with respect to the first side surface, and the first electronic device and the second electronic device are positioned such that the first and second side electrodes of the first electronic device are arrayed in substantially a straight line with the first and second side electrodes of the second electronic device and that the first side electrode of the first electronic device and the first side electrode of the second electronic device face each other and have substantially a same electric potential. 15 . The wiring board according to claim 1 , wherein the plurality of opening portions in the substrate forms spaces with respect to the plurality of electronic devices positioned in the plurality of opening portions, respectively, and the spaces are filled with a resin derived from the insulation layer. 16 . The wiring board according to claim 1 , wherein the plurality of opening portions includes at least one opening portion having tapered surfaces defining a space of the at least one opening portion. 17 . The wiring board according to claim 1 , wherein the plurality of electronic devices includes a chip capacitor having a dielectric body and an electrode formed the dielectric body such that the electrode extends from on an upper surface of the dielectric body to a lower surface of the dielectric body through a side surface of the dielectric body. 18 . The wiring board according to claim 1 , further comprising an opposing conductive pattern formed on an opposite surface of the boundary portion with respect to the conductive pattern on the surface of the boundary portion, wherein the boundary portion does not have a though-hole conductor connecting the conductive pattern formed on the surface of the boundary portion and the opposing conductive pattern formed on the opposite surface of the boundary portion. 19 . The wiring board according to claim 1 , wherein the substrate is an insulative substrate having a built-in metal sheet built in the insulative substrate. 20 . A method for manufacturing a wiring board, comprising: preparing a substrate; forming a plurality of opening portions in the substrate such that at least one boundary portion separating the opening portions is formed in the substrate and has a width which is in a range of approximately 0.05 to approximately 2.0 mm; forming a conductive pattern on the boundary portion of the substrate; positioning a plurality of electronic devices in the plurality of opening portions, respectively; and forming an insulation layer on the substrate and the conductive pattern on the boundary portion of the substrate such that the insulation layer covers the plurality of electronic devices in the plurality of opening portions of the substrate.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • on encapsulations · CPC title

  • On different surfaces · CPC title

  • of die-attach connectors · CPC title

  • comprising holes having chips therein · CPC title

Patent family

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Frequently asked questions

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What does patent US2015382471A1 cover?
A wiring board includes a substrate which has multiple opening portions and one or more boundary portions separating the opening portions, multiple electronic devices positioned in the opening portions of the substrate, respectively, a conductive pattern formed on a surface of the boundary portion, and an insulation layer formed on the substrate and the conductive pattern on the boundary portio…
Who is the assignee on this patent?
Ibiden Co Ltd
What technology area does this patent fall under?
Primary CPC classification H05K1/186. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).