Methods for forming recesses in source/drain regions and devices formed thereof
US-12132089-B2 · Oct 29, 2024 · US
Semiconductor device and fabrication method thereof
US2015340407A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2015340407-A1 |
| Application number | US-201514813530-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jul 30, 2015 |
| Priority date | Apr 12, 2013 |
| Publication date | Nov 26, 2015 |
| Grant date | — |
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Abstract
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A semiconductor device and a fabrication method thereof are provided The semiconductor device includes a local silicon-on-insulator (SOI) substrate in which a portion of a line-shaped active region is connected to a semiconductor substrate, and a remaining portion thereof is insulated from the semiconductor substrate, gate structures formed in a line shape to be substantially perpendicular to the active region on the active region insulated from the semiconductor substrate, and to surround a side and an upper surface of the active region, and having a stacking structure of a gate insulating layer, a liner conductive layer, a gate conductive layer, and a hard mask layer, a source region formed in the active region connected to the semiconductor substrate, and a drain region formed in the active region insulated from the semiconductor substrate between the gate structures.
First claim
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1 - 6 . (canceled) 7 . A method of fabricating a semiconductor device, the method comprising: providing a local silicon-on-insulator (SOI) substrate in which a portion of a line-shaped active region is connected to a semiconductor substrate, and a remaining portion thereof is insulated from the semiconductor substrate; forming gate structures on the remaining portion by sequentially forming a gate insulating layer, a liner conductive layer, a gate conductive layer, and a…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D64/667Primary
Electricity · mapped topic
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- What does patent US2015340407A1 cover?
- A semiconductor device and a fabrication method thereof are provided The semiconductor device includes a local silicon-on-insulator (SOI) substrate in which a portion of a line-shaped active region is connected to a semiconductor substrate, and a remaining portion thereof is insulated from the semiconductor substrate, gate structures formed in a line shape to be substantially perpendicular to t…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D64/667. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Nov 26 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).