Semiconductor device

US2015262922A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2015262922-A1
Application numberUS-201514593689-A
CountryUS
Kind codeA1
Filing dateJan 9, 2015
Priority dateMar 13, 2014
Publication dateSep 17, 2015
Grant date

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickness of the semiconductor chip is larger than a thickness from a lower surface of the die pad to a lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of each of the plurality of outer parts is larger than a thickness of the sealing body from a main surface of the semiconductor chip to an upper surface of the sealing body.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor device comprising: a die pad including a first surface and a second surface opposite to the first surface; a semiconductor chip including a main surface, a plurality of bonding electrodes formed on the main surface and a back surface opposite to the main surface, and mounted on the first surface of the die pad via a die bond material such that the back surface faces the first surface of the die pad; a plurality of leads electrically connected with the plurality of bonding electrodes via a plurality of wires, respectively; and a sealing body including an upper surface positioned on the main surface side of the semiconductor chip, a lower surface opposite to the upper surface and a side surface located between the upper surface and the lower surface, and sealing the die pad, the semiconductor chip and the plurality of wires such that a part of each of the plurality of leads protrudes from the side surface, wherein the part of each of the plurality of leads is bent on an outside of the sealing body, a thickness of the semiconductor chip is larger than a thickness from the second surface of the die pad to the lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of the part of each of the plurality of leads is larger than a thickness of the sealing body from the main surface of the semiconductor chip to the upper surface of the sealing body. 2 . The semiconductor device according to claim 1 , wherein the sealing body is made of thermosetting epoxy-based resin, the semiconductor chip includes a base material, made of silicon and a multilayer wiring layer that is formed on an element formation surface of the base material and thinner than the thickness of the base material, and a linear expansion coefficient of the semiconductor chip is smaller than a linear expansion coefficient of the sealing body. 3 . The semiconductor device according to claim 1 , wherein each of the plurality of leads includes a wire joint portion to which the wire is bonded, a first bending portion that is bent toward a thickness direction of the sealing body and a second bending portion that is bent toward a direction in parallel with the upper surface of the sealing body, and a distance from the lower surface of the sealing body to the second bending portion of each of the plurality of leads is larger than a thickness from an upper surface of the wire joint portion of each of the plurality of leads to the upper surface of the sealing body or a thickness from a lower surface of the wire joint portion of each of the plurality of leads to the lower surface of the sealing body. 4 . The semiconductor device according to claim 1 , wherein each of the plurality of leads includes a wire joint portion to which the wire is bonded, a first bending portion that is bent toward a thickness direction of the sealing body and a second bending portion that is bent toward a direction in parallel with the upper surface of the sealing body, the wire joint portion is sealed with the sealing body, each of the first bending portion and the second bending portion is exposed from the sealing body, the first bending portion is disposed so as to be spaced apart from the semiconductor chip compared with the wire joint portion, and the second bending portion is disposed so as to be spaced apart from the semiconductor chip compared with the first bending portion. 5 . The semiconductor device according to claim 1 , wherein the thickness of the semiconductor chip is larger than a thickness of the sealing body from the main surface of the semiconductor chip to the upper surface of the sealing body. 6 . The semiconductor device according to claim 1 , wherein a distance from the lower surface of the sealing body to the tip portion of the part of each of the plurality of leads is larger than the thickness of the semiconductor chip.

Assignees

Inventors

Classifications

  • comprising gold [Au] · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • characterised by their shape or disposition · CPC title

  • of bond wires · CPC title

  • of die-attach connectors · CPC title

Patent family

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2015262922A1 cover?
A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickne…
Who is the assignee on this patent?
Renesas Electronics Corp
What technology area does this patent fall under?
Primary CPC classification H10W70/421. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).