Flash memory cell with capacitive coupling between a metal floating gate and a metal control gate
US-2015036437-A1 · Feb 5, 2015 · US
Simple and cost-free mtp structure
US2015221663A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2015221663-A1 |
| Application number | US-201514684305-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 10, 2015 |
| Priority date | Jun 27, 2013 |
| Publication date | Aug 6, 2015 |
| Grant date | — |
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Abstract
Official abstract text for this publication.
Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate, a first transistor having a select gate and a second transistor having a floating gate. The select and floating gates are adjacent to one another and disposed over a transistor well. The transistors include first and second S/D regions disposed adjacent to the sides of the gates. A control gate is disposed over a control well. The control gate is coupled to the floating gate and includes a control capacitor. An erase terminal is decoupled from the control capacitor and transistors.
First claim
Opening claim text (preview).
What is claimed is: 1 . A non-volatile (NV) multi-time programmable (MTP) memory cell comprising: a substrate; a first transistor having a select gate and a second transistor having a floating gate adjacent to one another and disposed over a transistor well, the transistors comprise first and second S/D regions disposed adjacent to the sides of the gates; a control gate disposed over a control well, wherein the control gate is coupled to the floating gate, the control gate c…
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Physics · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US2015221663A1 cover?
- Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate, a first transistor having a select gate and a second transistor having a floating gate. The select and floating gates are adjacent to one another and disposed over a transistor well. The transistors include first and second S/D regions …
- Who is the assignee on this patent?
- Globalfoundries Sg Pte Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/0411. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Aug 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).