Packet switching

Patent metadata

Field	Value
Publication number	US-2015195206-A1
Application number	US-201414563267-A
Country	US
Kind code	A1
Filing date	Dec 8, 2014
Priority date	Jun 24, 2008
Publication date	Jul 9, 2015
Grant date	—

Abstract

In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

First claim

What is claimed is:

1 - 20 . (canceled)

21 . An apparatus comprising: at least one integrated circuit chip comprising:
at least one processor to execute switch control instructions; and switch circuitry to:
determine flow information from a received packet;
access packet processing policy information associated with the flow information;
determine whether to block the packet based on at least a portion of the flow information and at least a portion of the packet processing policy information;
determine at least one action based upon at least a portion of the flow information and at least a portion of the packet processing policy information; and
execute the at least one action.

22 . The apparatus of claim 21 , wherein the packet processing policy information is to implement flow-based quality of service through, at least in part, the at least one action.

23 . The apparatus of claim 21 , wherein the packet processing policy information is to implement Ethernet header-based quality of service through, at least in part, the at least one action.

24 . The apparatus of claim 21 , wherein the at least one action is to comprise selecting a queue from a plurality of queues and placing the packet in the selected queue.

25 . The apparatus of claim 21 , wherein the flow information is to comprise a source Medium Access Control (MAC) address of the packet.

26 . The apparatus of claim 21 , wherein the flow information is to comprise a destination MAC address of the packet.

27 . The apparatus of claim 21 , wherein the flow information is to comprise a source IP address of the packet.

28 . The apparatus of claim 21 , wherein the flow information is to comprise a destination IP address of the packet.

29 . The apparatus of claim 21 , wherein the flow information is to comprise a port of the packet.

30 . The apparatus of claim 21 , wherein the integrated circuit chip is to further comprise a content addressable memory to store at least a portion of the packet processing policy information.

31 . The apparatus of claim 21 , wherein the switch circuitry is to comprise programmable reconfigurable logic circuitry.

32 . The apparatus of claim 21 , wherein the packet processing policy information is to comprise a bit mask to be applied against at least a portion of the packet to determine whether at least one action specified by the packet processing policy information is to be executed in association with the packet.

33 . The apparatus of claim 21 , wherein the switching circuitry is to change the packet processing policy information in response to an instruction.

34 . The apparatus of claim 21 , wherein the at least one integrated circuit chip is a single integrated circuit chip.

35 . The apparatus of claim 21 , wherein the at least one processor is further to generate packet processing policy information.

36 . At least one machine readable storage medium having instructions stored thereon, the instructions when executed by a machine to cause the switch circuitry to:
determine flow information from a received packet; access packet processing policy information associated with the flow information; determine whether to block the packet based on at least a portion of the flow information and at least a portion of the packet processing policy information; determine at least one action based upon at least a portion of the flow information and at least a portion of the packet processing policy information; and execute the at least one additional action.

37 . The medium of claim 36 , wherein the packet processing policy information is to implement flow-based quality of service through, at least in part, the at least one action.

38 . The medium of claim 36 , wherein the packet processing policy information is to implement Ethernet header-based quality of service through, at least in part, the at least one action.

39 . The medium of claim 36 , wherein the at least one action is to comprise selecting a queue from a plurality of queues and placing the packet in the selected queue.

40 . The medium of claim 36 , wherein the flow information is to comprise a source Medium Access Control (MAC) address of the packet.

41 . The medium of claim 36 , wherein the flow information is to comprise a destination MAC address of the packet.

42 . The medium of claim 36 , wherein the flow information is to comprise a source IP address of the packet.

43 . The medium of claim 36 , wherein the flow information is to comprise a destination IP address of the packet.

44 . The medium of claim 36 , wherein the flow information is to comprise a port of the packet.

45 . The medium of claim 36 , wherein at least a portion of the packet processing policy information is stored in a content addressable memory.

46 . The medium of claim 36 , wherein the switch circuitry is to comprise programmable reconfigurable logic circuitry.

47 . The medium of claim 36 , wherein the packet processing policy information is to comprise a bit mask to be applied against at least a portion of the packet to determine whether at least one action specified by the packet processing policy information is to be executed in association with the packet.

48 . The medium of claim 36 , wherein the switching circuitry is to change the packet processing policy information in response to an instruction.

49 . A system comprising:
at least one host processor, a host processor comprising at least one processor core; machine-readable memory communicatively coupled to the at least one host processor; and at least one integrated circuit chip comprising:
at least one processor to execute switch control instructions; and
switch circuitry to:
determine flow information from a received packet;
access packet processing policy information associated with the flow information;
determine whether to block the packet based on at least a portion of the flow information and at least a portion of the packet processing policy information;
determine at least one action based upon at least a portion of the flow information and at least a portion of the packet processing policy information; and
execute the at least one action.

50 . The system of claim 49 , further comprising at least one network interface controller to receive the received packet.

Assignees

• Intel Corp

Inventors

• Memon Mazhar I
• King Steven R

Classifications

• H04L47/2433

  Allocation of priorities to traffic types · CPC title

• H04L47/2483

  involving identification of individual flows · CPC title

• H04L47/32

  by discarding or delaying data units, e.g. packets or frames · CPC title

• H04L47/2475

  for supporting traffic characterised by the type of applications · CPC title

• H04L47/6255

  queue load conditions, e.g. longest queue first · CPC title