Complementary metal-oxide-semiconductor (cmos) inverter circuit device

Patent metadata

Field	Value
Publication number	US-2015109047-A1
Application number	US-201414458628-A
Country	US
Kind code	A1
Filing date	Aug 13, 2014
Priority date	Oct 18, 2013
Publication date	Apr 23, 2015
Grant date	—

Abstract

There is provided a CMOS inverter circuit device. The CMOS inverter circuit device includes a delay circuit unit configured to generate different charge and discharge paths of each gate node of a PMOS transistor and an NMOS transistor respectively at the time that an input signal transitions between high and low levels. Therefore, the present examples minimize or erase generation of a short circuit current made at the time that the input signal transition. The examples may simplify circuit architecture, and may make a magnitude of a CMOS inverter circuit device smaller.

First claim

What is claimed is:

1 . A CMOS inverter circuit device, comprising:
a first P-type metal-oxide-semiconductor (PMOS) transistor and a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second PMOS transistor and a second NMOS transistor configured to: each receive an identical input signal through a gate terminal, and be connected in series respectively; a third PMOS transistor connected to a first node connected with drains of the first PMOS transistor and the first NMOS transistor; a third NMOS transistor connected to a second node connected with drains of the second PMOS transistor and the second NMOS transistor; and a delay circuit unit comprising: a fourth PMOS transistor and a fourth NMOS transistor configured to: each receive the input signal through a respective gate, and be connected in series in order for a fifth node connected with drains of the fourth PMOS transistor and the fourth NMOS transistor to be connected to a fourth node connected with a source of the first NMOS transistor and a source of the second PMOS transistor.

2 . The CMOS inverter circuit device of claim 1 ,
wherein the sources of the third PMOS transistor, first PMOS transistor and fourth PMOS transistor are connected to a power supply terminal, and wherein the sources of the third NMOS transistor, second NMOS transistor, and fourth NOMS transistor are connected to a ground terminal.

3 . The CMOS inverter circuit device of claim 2 ,
wherein a discharge path through the second NMOS transistor and a discharge path through the first NMOS transistor and fourth NMOS transistor are generated when the input signal is at a high level.

4 . The CMOS inverter circuit device of claim 3 ,
wherein the second node is discharged and the first node is discharged.

5 . The CMOS inverter circuit device of claim 4 ,
wherein the third PMOS transistor and third NMOS transistor are maintained in a turned-off state until the second node is discharged and the first node is discharged.

6 . The CMOS inverter circuit device of claim 2 ,
wherein a charge path through the first PMOS transistor and a charge path through the fourth PMOS transistor and second PMOS transistor are generated when the input signal is at a low level.

7 . The CMOS inverter circuit device of claim 6 ,
wherein the first node is charged and the second node is charged.

8 . The CMOS inverter circuit device of claim 7 ,
wherein the third PMOS transistor and third NMOS transistor are maintained in a turned-off condition until the first node is charged and the second node is charged.

9 . The CMOS inverter circuit device of claim 1 ,
wherein the fourth PMOS transistor and fourth NMOS transistor of the delay unit circuit comprise a connected a fifth PMOS transistor and a connected a fifth NMOS transistor connected in series.

10 . The CMOS inverter circuit device of claim 9 ,
wherein channel lengths of the fifth PMOS and fifth NMOS are the same as those of the fourth PMOS transistor and fourth NMOS transistor.

11 . The CMOS inverter circuit device of claim 9 ,
wherein the channel lengths of the fifth PMOS and fifth NMOS are different from those of the fourth PMOS transistor and fourth NMOS transistor.

12 . The CMOS inverter circuit device of claim 9 , wherein times of charging and discharging are controlled based on the number of the PMOS transistors and NMOS transistors of the delay unit circuit.

13 . A CMOS inverter circuit device, comprising:
a first P-type metal-oxide-semiconductor (PMOS) transistor and a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second PMOS transistor and a second NMOS transistor configured to: each receive an identical input signal through a gate terminal, and be connected in series respectively; a third PMOS transistor connected to a first node connected with drains of the first PMOS transistor and the first NMOS transistor; a third NMOS transistor connected to a second node connected with drains of the second PMOS transistor and the second NMOS transistor; and a delay circuit unit comprising: delay PMOS transistors and delay NMOS transistors configured to: each receive the input signal through a respective gate, and be connected in series in order for a fifth node connected with drains of the delay PMOS transistors and the delay NMOS transistors to be connected to a node connected with a source of the first NMOS transistor and a source of the second PMOS transistor.

14 . The CMOS inverter circuit device of claim 13 ,
wherein times of charging and discharging are controlled based on the number of the delay PMOS transistors and delay NMOS transistors of the delay unit circuit.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Ryu Beom Seon
• Lim Gyu Ho
• Kang Tae Kyoung

Classifications

• H03K19/00323

  Delay compensation · CPC title

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H03K19/0013 Primary

  in field effect transistor circuits · CPC title

• H03K19/0948 Primary

  using CMOS {or complementary insulated gate field-effect transistors} · CPC title

• H03K19/0175

  Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) · CPC title