Multi-threshold voltage FETs
US-9337109-B2 · May 10, 2016 · US
US2015073738A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2015073738-A1 |
| Application number | US-201314021284-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 9, 2013 |
| Priority date | Sep 9, 2013 |
| Publication date | Mar 12, 2015 |
| Grant date | — |
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Embodiments of the present invention relate to determining process variations using device threshold sensitivities. A computing device determines first and second threshold voltages for first and second transistors, respectively, wherein the first and second transistors are included in an integrated circuit and are n-channel and p-channel field effect transistors, respectively. The computing device also determines process parameters that are associated with the integrated circuit using a combination of determined first and second threshold voltages, wherein the process parameter reflects random sensitivities, timing delay differences, timing delay and slew rate changes, and/or variations between low, high, and regular threshold voltages which are associated with the first and second transistors.
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What is claimed is: 1 . A method comprising determining, by a computing device, first and second threshold voltages for first and second transistors, respectively, wherein the first and second transistors are included in an integrated circuit and are n-channel and p-channel field effect transistors, respectively; determining a process parameter associated with the integrated circuit using a combination of the determined first and second threshold voltages, wherein the process…
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Electricity · mapped topic
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