Current limiter circuit with adjustable response time
US-2024113517-A1 · Apr 4, 2024 · US
Semiconductor circuit
US2015048876A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2015048876-A1 |
| Application number | US-201414276088-A |
| Country | US |
| Kind code | A1 |
| Filing date | May 13, 2014 |
| Priority date | Aug 14, 2013 |
| Publication date | Feb 19, 2015 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
Provided is a semiconductor circuit. The semiconductor circuit includes: an input node configured to receive an enable signal, a sense enable signal, and a clock signal; and a clock gating circuit configured to output an enable clock signal corresponding to the clock signal while a signal level of the enable signal is at a first level regardless of a signal level of the sense enable signal, when the semiconductor circuit is in a high-voltage mode, and output an enable clock signal corresponding to the clock signal while a signal level of at least one of the enable signal and the sense enable signal is at the first level, when the semiconductor circuit is in a low-voltage mode.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor circuit comprising: an input node configured to receive an enable signal, a sense enable signal, and a clock signal; and a clock gating circuit configured to output an enable clock signal corresponding to the clock signal while a signal level of the enable signal is at a first level regardless of a signal level of the sense enable signal, when the semiconductor circuit is in a high-voltage mode, and output an enable clock signal correspo…
Assignees
Inventors
Classifications
- H03K17/284Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H03K19/0013Primary
Electricity · mapped topic
- H03K19/003Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2015048876A1 cover?
- Provided is a semiconductor circuit. The semiconductor circuit includes: an input node configured to receive an enable signal, a sense enable signal, and a clock signal; and a clock gating circuit configured to output an enable clock signal corresponding to the clock signal while a signal level of the enable signal is at a first level regardless of a signal level of the sense enable signal, whe…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H03K17/284. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Feb 19 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).