Frequency multiplier based on ring oscillator using power gating injection locking
US-2024267037-A1 · Aug 8, 2024 · US
Reference-frequency-insensitive phase locked loop
US2015048871A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2015048871-A1 |
| Application number | US-201414452204-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 5, 2014 |
| Priority date | Aug 19, 2013 |
| Publication date | Feb 19, 2015 |
| Grant date | — |
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Abstract
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A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the generated reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.
First claim
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What is claimed is: 1 . A method, comprising: in a phase locked loop: enabling, by the phase locked loop, usage of both rising and falling edges of a crystal clock signal generated by a crystal in the phase locked loop for an operation of the phase locked loop; and performing the operation of the phase locked loop based on the enabling. 2 . The method according to claim 1 , comprising: generating a reference clock signal whose frequency is twice a…
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- What does patent US2015048871A1 cover?
- A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the generated reference clock signal. The ph…
- Who is the assignee on this patent?
- Maxlinear Inc
- What technology area does this patent fall under?
- Primary CPC classification H03L7/093. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Feb 19 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).