Optoelectronic microdevice

Patent metadata

Field	Value
Publication number	US-12599047-B2
Application number	US-202118251502-A
Country	US
Kind code	B2
Filing date	Nov 12, 2021
Priority date	Nov 12, 2020
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

The present disclosure relates to development of microdevices on a substrate that can be released and transferred to a system substrate. The disclosure further relates to methods to integrate anchors to hold a microdevice to a substrate. The microdevices are in different configurations with respect to anchors, release layers, buffers layers and substrate.

First claim

The invention claimed is:

1 . A method to integrate anchors for holding microdevices to a substrate, the method comprising:
forming at least one microdevice on a first substrate wherein a release layer is deposited only on the at least one microdevice and patterned, and the release layer is extended at least from a part of a microdevice edge of the at least one microdevice; having pads on the microdevice on a top side away from the first substrate; covering microdevices by passivation layers; and covering the microdevice with a protection layer.

2 . The method of claim 1 , wherein parts of the passivation layers are patterned to form first and second anchors.

3 . The method of claim 2 , wherein a void structure is formed under a part of the anchor.

4 . The method of claim 1 , wherein there is a buffer layer between the microdevice and the first substrate.

5 . The method of claim 3 , wherein the microdevices are bonded to a second substrate using a bonding layer and a planarization layer.

6 . The method of claim 5 , wherein the first substrate and the buffer are removed, and a third anchor layer is deposited.

7 . The method of claim 6 , wherein the third anchor is a dielectric or a metal.

8 . The method of claim 6 , wherein the third anchor layer is a combination of multiple layers.

9 . The method of claim 6 , wherein the third anchor later is changing under different conditions such as temperature, electrical bias, or lights to push the microdevices forward.

10 . The method of claim 6 wherein the microdevices have pads on the bottom side and also have passivation layers.

11 . The method of claims 6 , wherein the microdevices are bonded to a third substrate and removed from the second substrate.

12 . The method of claim 11 , wherein the planarization layer and the first bonding layer are removed, and the anchors are patterned.

13 . The method of claim 12 , wherein the microdevices are covered by a second protection layer during removal of the release layer.

14 . The method of claim 13 , wherein the second protection layer is a photoresist.

15 . A method to integrate anchors for holding a microdevice to a substrate, the method comprising:
forming at least two anchors around each microdevice wherein a release layer is formed under each microdevice, and the release layer is extended at least from a part of a microdevice edge; and having the anchors for the adjacent microdevices offsetted.

16 . A method to integrate anchors to hold a microdevice to a substrate, the method comprising;
forming an anchor on a top of a substrate; separating at least a part of the anchor from the substrate with a release layer deposited only on the microdevice and wherein the release layer is extended at least from a part of a microdevice edge; and coupling the microdevice to the anchor with a bonding agent.

17 . The method of claim 16 where the release layer is removed or deformed to enable the microdevice to be separated from the substrate.

18 . The method of claim 16 , wherein the anchor and release layer are formed on the substrate and bonding the microdevice to the anchor.

Assignees

• Vuereal Inc

Inventors

• Chaji Gholamreza
• Siboni Hossein Zamani
• Fathi Ehsanollah

Classifications

• H10H20/0364

  of interconnections · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10F39/103 Primary

  the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10K71/80

  using temporary substrates · CPC title