Wide bandgap transistor layout with staggered gate electrode fingers and split active regions

Patent metadata

Field	Value
Publication number	US-12598800-B2
Application number	US-202318370120-A
Country	US
Kind code	B2
Filing date	Sep 19, 2023
Priority date	Sep 30, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A transistor comprising a first drain region split into first and second drain sub-regions aligned lengthwise and separated by a first low conductivity region, a first source region disposed on a first side of the first drain region split into first and second source sub-regions aligned lengthwise and separated by a second low conductivity region, a second source region disposed on a second side of the first drain region opposite the first side, the second source region split into third and fourth source sub-regions aligned lengthwise and separated by a third low conductivity region, a first gate electrode finger disposed over first and second active regions between the first drain region and first source region, and a second gate electrode finger disposed over third and fourth active regions between the first drain region and second source region.

First claim

What is claimed is:

1 . A transistor comprising:
a first drain region split into first and second drain sub-regions aligned lengthwise and separated by a first low conductivity region; a first source region disposed on a first side of the first drain region split into first and second source sub-regions aligned lengthwise and separated by a second low conductivity region; a second source region disposed on a second side of the first drain region opposite the first side, the second source region split into third and fourth source sub-regions aligned lengthwise and separated by a third low conductivity region; a first gate electrode finger disposed over first and second active regions between the first drain region and first source region; and a second gate electrode finger disposed over third and fourth active regions between the first drain region and second source region.

2 . The transistor of claim 1 wherein the second source region is displaced in a widthwise direction from the first source region.

3 . The transistor of claim 2 further comprising a second drain region on a side of the second source region opposite the first drain region, the second drain region aligned widthwise with the first drain region, the second drain region split into third and fourth drain sub-regions separated by a fourth low conductivity region, a fifth active region defined between the third drain sub-region and the second source region, a sixth active region defined between the fourth drain sub-region and the second source region.

4 . The transistor of claim 3 further comprising a third source region on a side of the second drain region opposite the second source region, the third source region aligned widthwise with the first source region and displaced widthwise from the second source region, the third source region split into fifth and sixth source sub-regions aligned lengthwise and separated by a fifth low conductivity region, a seventh active region defined between the fifth source sub-region and the second drain region, and eighth active region defined between the sixth source sub-region and the second drain region.

5 . The transistor of claim 4 wherein each of the first source region, the second source region, and the third source region have same widths.

6 . The transistor of claim 5 wherein the first active region, the second active region, the third active region, and the fourth active region have same widths.

7 . The transistor of claim 6 wherein each of the first and second active regions are displaced widthwise from each of the third and fourth active regions.

8 . The transistor of claim 6 wherein the first and second active regions are aligned widthwise with the fifth and sixth active regions, respectively.

9 . The transistor of claim 4 wherein the first drain region has a same width as the second drain region.

10 . The transistor of claim 9 wherein the first drain region includes a first widthwise extension on a second side of the first drain region opposite the first side of the first drain region, the first widthwise extension having a smaller length than the length of a remainder of the first drain region, a region between the first widthwise extension and the second source region including the third active region.

11 . The transistor of claim 10 wherein the second drain region includes a second widthwise extension on a same side of the second drain region as the second source region, the second widthwise extension having a smaller length than the length of a remainder of the second drain region, a region between the second widthwise extension and the second source region including the seventh active region.

12 . The transistor of claim 11 wherein the first drain region and the second drain region are symmetric about the second source region.

13 . The transistor of claim 4 further comprising a first drain bond pad disposed at a position displaced in a widthwise direction from the first source region and at least partially aligned in a lengthwise direction with the first source region.

14 . The transistor of claim 13 further comprising a second drain bond pad disposed at a position displaced in a widthwise direction from the third source region and at least partially aligned in a lengthwise direction with the third source region, and a drain tie electrically connecting the first drain bond pad to the second drain bond pad, the drain tie at least partially aligned in a lengthwise direction with the second source region.

15 . The transistor of claim 14 wherein a portion of the second source region is disposed between the first drain bond pad and the second drain bond pad.

16 . The transistor of claim 15 wherein portions of the second active region and third active region are disposed between portions of the first drain bond pad and second drain pond pad.

17 . The transistor of claim 4 further comprising a first gate bond pad at least partially aligned in a widthwise direction with the second source region.

18 . The transistor of claim 17 wherein the first gate bond pad is disposed at least partially between portions of the first source region and the third source region.

19 . The transistor of claim 17 further comprising a second gate bond pad on an opposite side of the first source region from the first gate bond pad, the first gate bond pad and second gate bond pad being electrically connected to one another.

20 . The transistor of claim 19 wherein portions of the first active region and the fourth active region are disposed between portions of the first gate bond pad and the second gate bond pad.

Assignees

• Skyworks Solutions Inc

Inventors

• Blin Guillaume Alexandre
• Zhu Yu

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/411

  for FETs · CPC title

• H10D64/257 Primary

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title