Nanosheet epitaxy with full bottom isolation

Patent metadata

Field	Value
Publication number	US-12598776-B2
Application number	US-202117457448-A
Country	US
Kind code	B2
Filing date	Dec 3, 2021
Priority date	Dec 3, 2021
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

Semiconductor channel layers vertically aligned and stacked one on top of another, separated by a gate stack material wrapping around the semiconductor channel layers, a heavily doped p-type field effect transistor (p-FET) source drain epitaxy region adjacent to the semiconductor channel layers, a horizontal lower surface of the p-FET source drain epitaxy region is adjacent to a horizontal upper surface of an undoped silicon epitaxy. Forming a first stack, second stack and third stack of nanosheet layers on a substrate, each including alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked one on top of another, forming a first sacrificial gate across the first stack, a second sacrificial gate across the second stack and a third sacrificial gate across the third stack, forming an undoped silicon epitaxy between the first and the second stacks and between the second and the third stacks.

First claim

What is claimed is:

1 . A semiconductor gate-all-around device comprising:
semiconductor channel layers vertically aligned and stacked one on top of another, the semiconductor channel layers separated from each other by a gate stack material wrapping around the semiconductor channel layers; and a heavily doped p-type field effect transistor (p-FET) source drain epitaxy region adjacent to the semiconductor channel layers, wherein a horizontal lower surface of the p-FET source drain epitaxy region is adjacent to a horizontal upper surface of an undoped silicon epitaxy, and wherein the p-FET source drain epitaxy is a same width as the undoped silicon epitaxy.

2 . The semiconductor gate-all-around device according to claim 1 , further comprising:
a bottom isolation region aligned below the undoped silicon epitaxy and below the semiconductor channel layers, wherein a topmost surface of the bottom isolation is below the undoped silicon epitaxy.

3 . The semiconductor gate-all-around device according to claim 1 , further comprising:
a heavily doped n-type field effect transistor (n-FET) source drain epitaxy doped region adjacent to a second set of semiconductor channel layers, wherein a horizontal lower surface of the n-FET source drain epitaxy region is adjacent to the horizontal upper surface of the undoped silicon epitaxy.

4 . The semiconductor gate-all-around device according to claim 1 , wherein
an upper horizontal surface of the undoped silicon epitaxy is below a lower horizontal surface of a lowermost channel layer of the semiconductor channel layers.

5 . The semiconductor gate-all-around device according to claim 1 , further comprising:
an inner spacer surrounding the gate stack material, the gate stack material wrapping around the semiconductor channel layers, and adjacent to the heavily doped source drain epitaxy region.

6 . The semiconductor gate-all-around device according to claim 1 , wherein
each of the semiconductor channel layers comprise an edge having a first height and an interior having a second height, and wherein the first height is greater than the second height.

7 . A semiconductor device comprising:
a first set of semiconductor channel layers vertically aligned and stacked one on top of another; a heavily doped p-type field effect transistor (p-FET) source drain epitaxy region adjacent to the first set of semiconductor channel layers, wherein a horizontal lower surface of the p-FET source drain epitaxy region is adjacent to a horizontal upper surface of an undoped silicon epitaxy; a heavily doped n-type field effect transistor (n-FET) source drain epitaxy doped region adjacent to a second set of semiconductor channel layers, wherein a horizontal lower surface of the n-FET source drain epitaxy region is adjacent to the horizontal upper surface of the undoped silicon epitaxy; a bottom isolation region aligned below the undoped silicon epitaxy and below the semiconductor channel layers; and a seed layer separating the bottom isolation and undoped silicon epitaxy.

8 . The semiconductor device according to claim 7 , further comprising a gate stack material wrapping around the first set of semiconductor channel layers, and wherein the undoped silicon epitaxy is horizontally separated from the gate stack material by an inner spacer.

9 . The semiconductor device according to claim 7 , wherein
an upper horizontal surface of the undoped silicon epitaxy is below a lower horizontal surface of a lowest channel layer of the semiconductor channel layers.

10 . The semiconductor device according to claim 8 , wherein
the inner spacer surrounding gate stack material, the gate stack material wrapping around the semiconductor channel layers, and adjacent to the heavily doped p-FET source drain epitaxy region.

11 . The semiconductor device according to claim 10 , wherein
each of the semiconductor channel layers comprise an edge having a first height and an interior having a second height, and wherein the first height is greater than the second height.

12 . The semiconductor device according to claim 7 , wherein
a lower surface of a conductive trench contact is adjacent to an upper surface of a portion of the source drain epitaxy region.

13 . A method comprising:
forming a first stack of nanosheet layers on a substrate, a second stack of nanosheet layers on the substrate, and a third stack of nanosheet layers on the substrate, the first stack, the second stack and the third stack of nanosheet layers each comprising alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked one on top of another; forming a first sacrificial gate across the first stack of nanosheet layers, a second sacrificial gate across the second stack of nanosheet layers and a third sacrificial gate across the third stack of nanosheet layers; and forming an undoped silicon epitaxy between the first stack and the second stack of nanosheet layers and between the second stack and the third stack of nanosheet layers.

14 . The method according to claim 13 , further comprising:
after forming the undoped silicon epitaxy between the first stack and the second stack of nanosheet layers and between the second stack and the third stack of nanosheet layers, replacing a sacrificial epitaxial layer under the first stack, second stack and third stack of nanosheet layers and under the undoped silicon epitaxy, with a continuous bottom dielectric isolation.

15 . The method according to claim 14 , further comprising:
replacing a portion of the undoped silicon epitaxy between the first stack and the second stack of nanosheet layers with a heavily p-type field effect transistor (p-FET) source drain epitaxy region; and replacing a portion of the undoped silicon epitaxy between the second stack and the third stack of nanosheet layers with a heavily n-type field effect transistor (n-FET) source drain epitaxy region.

16 . The method according to claim 13 , further comprising:
replacing the first, second and third sacrificial gate with a first, second and third gate stack.

17 . The method according to claim 13 , further comprising:
after forming the undoped silicon epitaxy between the first stack and the second stack of nanosheet layers and between the second stack and the third stack of nanosheet layers, replacing a sacrificial epitaxial layer under the first stack and second stack of nanosheet layers and under the undoped silicon epitaxy between the first stack and the second stack of nanosheet layers with a first continuous bottom dielectric isolation; and replacing a sacrificial epitaxial layer under the third stack of nanosheet layers and under the undoped silicon epitaxy between the second stack and the third stack of nanosheet layers with a second continuous bottom dielectric isolation.

18 . The method according to claim 17 , further comprising:
replacing the undoped silicon epitaxy between the first stack and the second stack of nanosheet layers with a heavily p-type field effect transistor (p-FET) source drain epitaxy region; and replacing a portion of the undoped silicon epitaxy between the second stack and the third stack of nanosheet layers with a heavily n-type field effect transistor (n-FET) source drain epitaxy region.

19 . The method according to claim 13 , wherein
an upper horizontal surface of the undoped silicon epitaxy is below a lower horizontal surface of a lowest channel layer of the first stack of nanosheet layers.

20 . The method acc

Assignees

• Int Business Machines Corporation

Inventors

• Frougier Julien
• Greene Andrew M
• Xie Ruilong
• Yu Lan
• Montanini Pietro

Classifications

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title