Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12598769-B2
Application number	US-202318128253-A
Country	US
Kind code	B2
Filing date	Mar 30, 2023
Priority date	Dec 20, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A semiconductor device and a manufacturing method thereof are disclosed in the present invention. The semiconductor device includes a source structure; a gate structure disposed above the source structure; a first opening penetrates through the gate structure in a vertical direction; a semiconductor structure; a gate dielectric layer; an insulation structure; and a void. The semiconductor structure is partially disposed in the first opening, and at least a portion of the gate structure is located at two opposite sides of the semiconductor structure in a horizontal direction. The gate dielectric layer is disposed in the first opening and located between the semiconductor structure and the gate structure. At least a portion of the insulation structure is disposed in the first opening, at least a portion of the semiconductor structure is located between the insulation structure and the gate dielectric layer, and the void is located in the insulation structure.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a source structure; a gate structure disposed above the source structure; a first opening penetrating through the gate structure in a vertical direction; a semiconductor structure partially disposed in the first opening, wherein at least a portion of the gate structure is located at two opposite sides of the semiconductor structure in a horizontal direction; a gate dielectric layer disposed in the first opening and located between the semiconductor structure and the gate structure; an insulation structure, wherein at least a portion of the insulation structure is disposed in the first opening, and at least a portion of the semiconductor structure is located between the insulation structure and the gate dielectric layer; and a void located in the insulation structure.

2 . The semiconductor device according to claim 1 , wherein the gate dielectric layer comprises:
a first portion extending in the vertical direction; and a second portion extending in the horizontal direction and disposed between the semiconductor structure and the source structure in the vertical direction.

3 . The semiconductor device according to claim 1 , further comprising:
a dielectric layer disposed between the gate structure and the source structure in the vertical direction; and a bottom semiconductor layer disposed between the dielectric layer and the source structure in the vertical direction, wherein the semiconductor structure penetrates through the dielectric layer in the vertical direction for physically contacting the bottom semiconductor layer.

4 . The semiconductor device according to claim 3 , further comprising:
a second opening penetrating through the dielectric layer in the vertical direction, wherein the second opening is connected with the first opening, and the semiconductor structure physically contacts the bottom semiconductor layer via the second opening.

5 . The semiconductor device according to claim 4 , wherein the void is partly located in the first opening and partly located in the second opening.

6 . The semiconductor device according to claim 4 , wherein the semiconductor structure comprises:
a first semiconductor layer disposed in the first opening; a second semiconductor layer partly disposed in the first opening and partly disposed in the second opening, wherein the first semiconductor layer surrounds the second semiconductor layer in the horizontal direction, and the second semiconductor layer physically contacts the bottom semiconductor layer; and a third semiconductor layer disposed on the insulation structure in the vertical direction, wherein the second semiconductor layer surrounds the third semiconductor layer in the horizontal direction, and the second semiconductor layer physically contacts the first semiconductor layer and the third semiconductor layer.

7 . The semiconductor device according to claim 6 , wherein a portion of the second semiconductor layer is located between the bottom semiconductor layer and the insulation structure in the vertical direction.

8 . The semiconductor device according to claim 1 , wherein a portion of the semiconductor structure is located between the void and the insulation structure.

9 . The semiconductor device according to claim 1 , wherein the void is lower than an upper surface of the insulation structure in the vertical direction.

10 . The semiconductor device according to claim 1 , wherein the void is connected with an upper surface of the insulation structure.

11 . The semiconductor device according to claim 1 , further comprising:
a drain structure disposed on the semiconductor structure and the gate dielectric layer, wherein a portion of the semiconductor structure is located between the insulation structure and the drain structure in the vertical direction.

12 . A manufacturing method of a semiconductor device, comprising:
forming a gate structure above a source structure; forming a first opening penetrating through the gate structure in a vertical direction; forming a gate dielectric layer in the first opening; forming an insulation structure, wherein at least a portion of the insulation structure is formed in the first opening; and forming a semiconductor structure partially in the first opening, wherein a void is located in the insulation structure, at least a portion of the gate structure is located at two opposite sides of the semiconductor structure in a horizontal direction, the gate dielectric layer is located between the semiconductor structure and the gate structure, and at least a portion of the semiconductor structure is located between the insulation structure and the gate dielectric layer.

13 . The manufacturing method of the semiconductor device according to claim 12 , further comprising:
forming a bottom semiconductor layer on the source structure before the step of forming the gate structure; and forming a dielectric layer on the bottom semiconductor layer, wherein the bottom semiconductor layer is located between the dielectric layer and the source structure in the vertical direction, and the dielectric layer is located between the gate structure and the bottom semiconductor layer in the vertical direction.

14 . The manufacturing method of the semiconductor device according to claim 13 , wherein a method of forming the semiconductor structure comprises:
forming a first semiconductor layer on the gate dielectric layer; and forming a second opening penetrating through the dielectric layer in the vertical direction, wherein the second opening is connected with the first opening, and a portion of the first semiconductor layer and a portion of the gate dielectric layer are removed by a process of forming the second opening.

15 . The manufacturing method of the semiconductor device according to claim 14 , wherein the method of forming the semiconductor structure further comprises:
forming a second semiconductor layer after the step of forming the second opening, wherein the second semiconductor layer is partly formed in the first opening and partly formed in the second opening, and the second semiconductor layer physically contacts the bottom semiconductor layer.

16 . The manufacturing method of the semiconductor device according to claim 15 , wherein a portion of the second semiconductor layer is located between the bottom semiconductor layer and the insulation structure in the vertical direction.

17 . The manufacturing method of the semiconductor device according to claim 15 , wherein a method of forming the insulation structure comprises:
forming an insulation material on the second semiconductor layer after the second semiconductor layer is formed; and performing an etching back process to the insulation material for removing a portion of the insulation material and forming the insulation structure.

18 . The manufacturing method of the semiconductor device according to claim 17 , wherein the method of forming the semiconductor structure further comprises:
forming a third semiconductor layer on the insulation structure, wherein the second semiconductor layer physically contacts the first semiconductor layer and the third semiconductor layer, and the semiconductor structure comprises the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.

19 . The manufacturing method of the semiconductor device according to claim 12 , wherein the gate dielectric layer comprises:
a first portion extending in t

Assignees

• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Kong Guoguo
• Wu Gang
• Ge Mingru
• He Shiwei
• Chu Hsien-Shih
• Chen Junkun

Classifications

• H10P50/283

  by chemical means · CPC title

• H10D30/025 Primary

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D30/63 Primary

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H01L21/31111

  Electricity · mapped topic