Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12598736-B2
Application number	US-202318151534-A
Country	US
Kind code	B2
Filing date	Jan 9, 2023
Priority date	May 12, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base and a capacitor structure. The base is provided with a capacitive contact structure. The capacitor structure is connected to the capacitive contact structure, and the capacitor structure includes a plurality of capacitor units stacked in a direction vertical to the capacitive contact structure.

First claim

The invention claimed is:

1 . A semiconductor structure, comprising:
a base, wherein the base is provided with at least two capacitive contact structures; at least two capacitor structures, wherein each capacitor structure is connected to each capacitive contact structure, the capacitor structure comprises a plurality of capacitor units stacked in a direction vertical to the capacitive contact structure; and a support structure, located between adjacent capacitor structures, wherein the support structure comprises: an auxiliary conductive portion and a support portion alternately arranged in a vertical direction perpendicular to the base, the support portion is located between adjacent capacitor units in the direction parallel to the base.

2 . The semiconductor structure according to claim 1 , wherein the capacitor unit comprises: a capacitive connection structure, a first electrode, a second electrode, and a high-K dielectric layer;
the capacitive connection structure is located vertically above the capacitive contact structure, and in any adjacent two of the capacitor units in the direction vertical to the capacitive contact structure, the capacitive connection structures are interconnected and connected to the capacitive contact structure; the first electrode is located on a sidewall of the capacitive connection structure, and in any adjacent two of the capacitor units in the direction vertical to the capacitive contact structure, the first electrodes are interconnected; the high-K dielectric layer is arranged on a sidewall of the first electrode, and in any adjacent two of the capacitor units in the direction vertical to the capacitive contact structure, the high-K dielectric layers are interconnected; and the second electrode is arranged on a sidewall of the high-K dielectric layer, and in any adjacent two of the capacitor units in the direction vertical to the capacitive contact structure, the second electrodes are interconnected.

3 . The semiconductor structure according to claim 2 , further comprising: a top dielectric layer covering the capacitor structure, and a common-source electrode layer located above the top dielectric layer,
wherein the top dielectric layer has an opening, and the common-source electrode layer is connected to the second electrode through the opening.

4 . The semiconductor structure according to claim 2 , wherein a plurality of capacitive contact structures are distributed in an array on the base, and in any adjacent two of the capacitor units in a direction parallel to the base, the second electrodes are interconnected;
wherein in any adjacent two of the capacitor units in the direction parallel to the base, bottom portions of the second electrodes are interconnected and form a groove; and the support structure is located in the groove.

5 . The semiconductor structure according to claim 4 , wherein an upper surface of the support structure away from the base is flush with a top surface of the second electrode away from the base;
wherein the auxiliary conductive portion is connected to the adjacent second electrode.

6 . The semiconductor structure according to claim 1 , wherein the capacitor unit comprises: a first electrode, a second electrode, and a high-K dielectric layer;
the first electrode is located vertically above the capacitive contact structure, and in any adjacent two of the capacitor units in the direction vertical to the capacitive contact structure, the first electrodes are interconnected and connected to the capacitive contact structure; the high-K dielectric layer is arranged on a sidewall of the first electrode, and in any adjacent two of the capacitor units in the direction vertical to the capacitive contact structure, the high-K dielectric layers are interconnected; and the second electrode is arranged on a sidewall of the high-K dielectric layer, and in any adjacent two of the capacitor units in the direction vertical to the capacitive contact structure, the second electrodes are interconnected; wherein a barrier layer is provided between the high-K dielectric layer and the first electrode.

7 . The semiconductor structure according to claim 6 , wherein the high-K dielectric layer in the capacitor unit in a top layer further covers a top surface of the first electrode away from the base, and the second electrode of the capacitor unit in the top layer further covers a top surface of the high-K dielectric layer away from the base; and
the semiconductor structure further comprises: a common-source electrode layer covering a sidewall of the second electrode and a top surface of the second electrode away from the base.

8 . The semiconductor structure according to claim 6 , wherein a plurality of capacitive contact structures are distributed in an array on the base, and in any adjacent two of the capacitor units in a direction parallel to the base, the second electrodes are interconnected.

9 . A method of manufacturing a semiconductor structure, comprising:
providing a base, wherein the base is provided with at least two capacitive contact structures; and forming at least two capacitor structures and a support structure, wherein each capacitor structure is connected to each capacitive contact structure, the capacitor structure comprises a plurality of capacitor units stacked in a direction vertical to the capacitive contact structure, the support structure is located between adjacent capacitor structures, and the support structure comprises: an auxiliary conductive portion and a support portion alternately arranged in a vertical direction perpendicular to the base, the support portion is located between adjacent capacitor units in the direction parallel to the base.

10 . The method of manufacturing the semiconductor structure according to claim 9 , wherein the stacking a plurality of capacitor units in a direction vertical to the capacitive contact structure to form a capacitor structure comprises:
forming a bottom capacitor unit vertically above the capacitive contact structure, comprising: forming a capacitive connection structure vertically above the capacitive contact structure, and sequentially forming a first electrode, a high-K dielectric layer, and a second electrode on a sidewall of the capacitive connection structure; stacking an intermediate capacitor unit layer by layer vertically above the bottom capacitor unit, wherein forming the intermediate capacitor unit in an (N+1)-th layer comprises: forming a capacitive connection structure of the (N+1)-th layer vertically above a capacitive connection structure of an N-th layer, and sequentially forming a first electrode, a high-K dielectric layer, and a second electrode on a sidewall of the capacitive connection structure of the (N+1)-th layer, wherein N is a positive integer, and 2≤N+1≤M; and stacking a top capacitor unit vertically above the intermediate capacitor unit, comprising: forming a capacitive connection structure of an (M+1)-th layer vertically above a capacitive connection structure of an M-th layer, and sequentially forming a first electrode, a high-K dielectric layer, and a second electrode on a sidewall of the capacitive connection structure of the (M+1)-th layer; wherein the capacitive connection structure is formed through an epitaxial growth process.

11 . The method of manufacturing the semiconductor structure according to claim 10 , further comprising:
forming a top dielectric material layer covering the top capacitor unit; patterning the top dielectric material layer to form a top dielectric layer, wherein the top dielectric layer has an opening, and the second electrode of the top capacitor unit is exposed from the opening; and

Assignees

• Changxin Memory Tech Inc

Inventors

• Huang Juanjuan
• Bai Weiping

Classifications

• H10D1/716

  having vertical extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title