Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12598735-B2
Application number	US-202318152224-A
Country	US
Kind code	B2
Filing date	Jan 10, 2023
Priority date	May 5, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a substrate, a first dielectric layer, a second dielectric layer, and a gate structure, where an active region is provided in the substrate, and a source region of a first doping type and a drain region of the first doping type are disposed in the active region; the first dielectric layer is disposed on the substrate and covers a part of the source region and/or a part of the drain region; the second dielectric layer is disposed on the substrate and connected to the first dielectric layer, a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer.

First claim

The invention claimed is:

1 . A semiconductor structure, comprising:
a substrate, wherein an active region is provided in the substrate, and a source region of a first doping type and a drain region of the first doping type are disposed in the active region; a first dielectric layer, disposed on the substrate and covering at least one of a part of the source region or a part of the drain region; a second dielectric layer, disposed on the substrate, wherein the first dielectric layer is connected to the second dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer; and a gate structure, wherein orthographic projection of the gate structure on the substrate covers orthographic projections of the second dielectric layer and the first dielectric layer on the substrate; the gate structure comprises a gate layer, the gate layer is disposed on the second dielectric layer, and an overlapping region exists between projection of the gate layer on the substrate and the projection of the first dielectric layer on the substrate; the first dielectric layer comprises a first dielectric sublayer and an air gap, at least part of the air gap is located below the gate layer, and the air gap is located between the first dielectric sublayer and the second dielectric layer.

2 . The semiconductor structure according to claim 1 , wherein
the dielectric constant of the first dielectric layer is smaller than or equal to 3.

3 . The semiconductor structure according to claim 1 , wherein
the dielectric constant of the second dielectric layer is greater than or equal to 3.9.

4 . The semiconductor structure according to claim 1 , wherein
the first dielectric layer is as thick as the second dielectric layer.

5 . The semiconductor structure according to claim 1 , wherein
the gate structure further comprises protection structures; and the protection structures are disposed at two sides of the gate layer, and cover side surfaces of the gate layer.

6 . The semiconductor structure according to claim 5 , wherein
each of the protection structures comprises an isolation layer and a protective layer; the isolation layer is disposed on a sidewall of the gate layer; and the protective layer is disposed on a sidewall of the isolation layer, and is away from the gate layer.

7 . The semiconductor structure according to claim 1 , wherein
the substrate further comprises a channel region of a second doping type, the channel region is disposed below the gate structure, and is connected to the source region and the drain region, and the second dielectric layer covers a top surface of the channel region.

8 . The semiconductor structure according to claim 1 , wherein
the substrate further comprises at least one of a first source subregion of the first doping type or a first drain subregion of the first doping type, the first source subregion is located at one side of the source region and close to the drain region, the first drain subregion is located at one side of the drain region and close to the source region, a dopant ion concentration of the first source subregion is smaller than a dopant ion concentration of the source region, and a dopant ion concentration of the first drain subregion is smaller than a dopant ion concentration of the drain region.

Assignees

• Changxin Memory Tech Inc
• Changxin Jidian Beijing Memory Tech Co Ltd

Inventors

• Lv Zhaohong

Classifications

• H10B12/05 Primary

  Making the transistor · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title

• H10B12/30 Primary

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10D64/01

  Manufacture or treatment · CPC title