Memory device and method for fabricating same

Patent metadata

Field	Value
Publication number	US-12598730-B2
Application number	US-202217976849-A
Country	US
Kind code	B2
Filing date	Oct 30, 2022
Priority date	Nov 15, 2021
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

Embodiments provide a memory device and a method for fabricating the same, relating to the field of semiconductor technology. The method includes: forming buried gate structures in a first direction in a substrate; patterning the substrate, cutting off the buried gate structures, and forming active structures arranged at parallel intervals and isolation grooves between the active structures in a second direction, where the active structures are island-shaped columnar bodies, and the active structures include the buried gate structures; forming isolation structures in the isolation grooves, where surfaces of the isolation structures are flush with surfaces of the active structures; and forming conductive word lines in the first direction on the surfaces of isolation structures and the surfaces of the active structures, where the conductive word lines cover upper surfaces of the buried gate structures in the active structures.

First claim

What is claimed is:

1 . A method for fabricating a memory device, comprising:
forming a plurality of buried gate structures in a first direction in a substrate; forming a first nitride layer on the surface of the substrate, and patterning the first nitride layer, to form a plurality of active area mask structures arranged at parallel intervals in the second direction; etching and removing the substrate exposed using the plurality of active area mask structures as etching masks, to cut off the plurality of buried gate structures, and form a plurality of active structures arranged at parallel intervals and isolation grooves between the plurality of active structures, wherein a depth of each of the plurality of active structures is greater than a depth of each of the plurality of buried gate structures; wherein the plurality of active structures are island-shaped columnar bodies, and the plurality of active structures comprise a plurality of remained buried gate structures; forming isolation structures in the isolation grooves, surfaces of the isolation structures being flush with surfaces of the plurality of active structures; and forming a plurality of conductive word lines in the first direction on the top surfaces of isolation structures and the top surfaces of the plurality of active structures, the plurality of conductive word lines covering upper surfaces of the plurality of buried gate structures in the plurality of active structures.

2 . The method for fabricating the memory device according to claim 1 , wherein the patterning the first nitride layer comprises:
forming a second mask layer on a top surface of the first nitride layer; patterning the second mask layer to form a strip-shaped mask in the second direction, and etching and removing the first nitride layer exposed using the second mask layer as an etching mask, such that the first nitride layer forms a strip-shaped structure in the second direction; and cutting off the strip-shaped mask in the second direction into an island-shaped mask having a preset length, and etching and removing the first nitride layer exposed using the island-shaped mask as an etching mask, such that the first nitride layer forms the plurality of active area mask structures arranged at parallel intervals.

3 . The method for fabricating the memory device according to claim 1 , wherein the forming the isolation structures in the isolation grooves comprises:
performing a chemical vapor deposition process to form the isolation structures in the isolation grooves; and planarizing top surfaces of the isolation structures and top surfaces of the plurality of active structures, such that the top surfaces of the isolation structures are flush with the top surfaces of the plurality of active structures.

4 . The method for fabricating the memory device according to claim 1 , wherein the forming the plurality of buried gate structures in the first direction in the substrate comprises:
forming a first mask layer on a surface of the substrate; patterning the first mask layer to form a plurality of first trenches in the first direction exposing the surface of the substrate; etching and removing part of the substrate below the plurality of first trenches using the first mask layer as an etching mask, to form a plurality of embedded word line trenches in the first direction; and filling a conductive material layer in each of the plurality of embedded word line trenches, such that an upper surface of the conductive material layer is flush with an upper surface of the substrate to form the plurality of buried gate structures.

5 . The method for fabricating the memory device according to claim 4 , wherein before filling the conductive material layers in the plurality of embedded word line trenches, the method further comprises: forming a gate dielectric layer on an inner wall of each of the plurality of embedded word line trenches.

6 . The method for fabricating the memory device according to claim 5 , wherein the gate dielectric layer comprises a silicon oxide layer, each of the conductive material layers comprises a tungsten conductive layer, and each of the isolation structures comprises a silicon oxide structure.

7 . The method for fabricating the memory device according to claim 1 , wherein the forming the plurality of conductive word lines in the first direction on the surfaces of the isolation structures and the surfaces of the plurality of active structures comprises:
forming conductive layers on the top surfaces of the isolation structures and the top surfaces of the plurality of active structures; and patterning the conductive layers to form the plurality of conductive word lines in the first direction and second trenches between the plurality of conductive word lines.

8 . The method for fabricating the memory device according to claim 7 , wherein the patterning the conductive layers to form the plurality of conductive word lines in the first direction and the second trenches between the plurality of conductive word lines comprises:
forming a second nitride layer on a top surface of each of the conductive layers; patterning the second nitride layer to expose part of the conductive layers; and etching and removing the conductive layers exposed using the second nitride layer as an etching mask, to form the plurality of conductive word lines in the first direction and the second trenches between the plurality of conductive word lines.

9 . The method for fabricating the memory device according to claim 7 , further comprising:
forming isolation layers, the isolation layers filling the second trenches and covering the plurality of conductive word lines.

10 . A memory device, comprising: a substrate, a plurality of buried gate structures formed on the substrate, isolation structures, a plurality of conductive word lines in a first direction, and a plurality of active structures arranged at parallel intervals in a second direction;
wherein the plurality of active structures are island-shaped columnar bodies, the isolation structures are embedded in isolation grooves between the plurality of active structures, and surfaces of the plurality of active structures are flush with surfaces of the isolation structures; wherein the plurality of buried gate structures are embedded in the plurality of active structures, and surfaces of the plurality of buried gate structures are flush with the surfaces of the plurality of active structures, and the plurality of buried gate structures are arranged at intervals in the first direction; and wherein the plurality of conductive word lines are in contact with top surfaces of the plurality of buried gate structures and top surfaces of the isolation structures, and the plurality of buried gate structures arranged along the first direction are electrically connected through a corresponding one of the conductive word lines.

11 . The memory device according to claim 10 , wherein bottoms of the plurality of buried gate structures are flush with each other.

12 . The memory device according to claim 10 , further comprising an isolation layer, wherein the isolation layer is formed on each of the plurality of conductive word lines and is filled between the plurality of conductive word lines.

13 . The memory device according to claim 10 , wherein each of the plurality of buried gate structures comprises an embedded word line trench and a conductive material layer, the conductive material layer filling the embedded word line trench, and a width of the embedded word line trench being greater than or equal to a width of each of the plurality of conductive word lines.

Assignees

• Changxin Memory Tech Inc

Inventors

• Lu Jingwen

Classifications

• H10B12/488 Primary

  Word lines · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/053

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title