Memory system, control method thereof, and program

Patent metadata

Field	Value
Publication number	US-12597475-B2
Application number	US-202418677727-A
Country	US
Kind code	B2
Filing date	May 29, 2024
Priority date	Mar 22, 2018
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.

First claim

What is claimed is:

1 . A memory system comprising:
a memory device including:
a nonvolatile memory cell array; and
a control circuit configured to execute a plurality of read methods; and
a memory controller configured to:
determine, on the basis of a writing mode used when read target data was written to the nonvolatile memory cell array, a read instruction to be outputted to the memory device to cause the control circuit to execute one of the plurality of read methods to read the read target data, the writing mode corresponding to the number of bits of a value stored in one memory cell of the nonvolatile memory cell array; and
output the determined read instruction to the memory device.

2 . The memory system according to claim 1 , wherein
the memory controller is configured to receive a read request designating the read target data from a host, and the determined read instruction is an initial read instruction of one or more read instructions outputted to the memory device in a read sequence corresponding to the read request.

3 . The memory system according to claim 1 , wherein
the plurality of read methods include at least a first read method and a second read method, and the memory controller is configured to:
in a case where the writing mode is a first mode, determine a first read instruction as the read instruction, the first read instruction being outputted to cause the control circuit to execute the first read method; and
in a case where the writing mode is a second mode which is different from the first mode, determine a second read instruction as the read instruction, the second read instruction being outputted to cause the control circuit to execute the second read method.

4 . The memory system according to claim 3 , wherein
the first mode is a single-level cell (SLC) mode or a multi-level cell (MLC) mode, and the second mode is a quad-level cell (QLC) mode.

5 . The memory system according to claim 4 , wherein
a first time period from when the first read instruction is outputted to the memory device until data read by executing the first read method becomes ready to be transferred from the memory device is shorter than a second time period from when the second read instruction is outputted to the memory device until data read by executing the second read method becomes ready to be transferred from the memory device.

6 . The memory system according to claim 4 , wherein
the memory device is configured to output ready-busy-state information to the memory controller, and a first time period during which the ready-busy-state information corresponding to the first read method indicates a busy state is shorter than a second time period during which the ready-busy-state information corresponding to the second read method indicates the busy state.

7 . The memory system according to claim 4 , wherein
the memory device takes a first time period to complete the first read method, and the memory device takes a second time period to complete the second read method, the second time period being longer than the first time period.

8 . The memory system according to claim 1 , wherein
the read instruction includes a first part indicating the one of the plurality of read methods, and at least the first part is based on the writing mode.

9 . The memory system according to claim 8 , wherein
the read instruction further includes a second part indicating a row address associated with the read target data and a third part indicating a column address associated with the read target data.

10 . The memory system according to claim 1 , wherein
the memory controller is further configured to receive a read request designating the read target data from a host, and the memory controller is configured to:
determine the read instruction, further on the basis of the number of read instructions previously outputted to the memory device in a read sequence corresponding to the read request.

11 . The memory system according to claim 1 , wherein
the memory controller is connected to the memory device via a bus, and the memory controller is further configured to output a command latch enable signal and an address latch enable signal to the memory device via the bus.

12 . A memory system comprising:
a memory device including:
a nonvolatile memory cell array; and
a control circuit configured to execute a plurality of read methods; and
a memory controller configured to:
determine, on the basis of a physical address associated with read target data, a read instruction to be outputted to the memory device to cause the control circuit to execute one of the plurality of read methods to read the read target data; and
output the determined read instruction to the memory device.

13 . The memory system according to claim 12 , wherein
the memory controller is configured to receive a read request designating the read target data from a host, and the determined read instruction is an initial read instruction of one or more read instructions outputted to the memory device in a read sequence corresponding to the read request.

14 . The memory system according to claim 12 , wherein
the plurality of read methods include at least a first read method and a second read method, the memory device further includes a substrate, the nonvolatile memory cell array includes a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation and including a plurality of memory cells at intersection locations of a plurality of word lines and a memory pillar, the plurality of word lines being stacked apart from each other in a first direction perpendicular to the substrate, the memory pillar passing through the plurality of word lines in the first direction, the plurality of word lines include:
a first word line which is closest to the substrate among the plurality of word lines;
a second word line adjacent to the first word line, and
the memory controller is configured to:
in a case where the physical address corresponds to the first word line, determine a first read instruction as the read instruction, the first read instruction being outputted to cause the control circuit to execute the first read method; and
in a case where the physical address corresponds to the second word line, determine a second read instruction as the read instruction, the second read instruction being outputted to cause the control circuit to execute the second read method.

15 . The memory system according to claim 14 , wherein
a first time period from when the first read instruction is outputted to the memory device until data read by executing the first read method becomes ready to be transferred from the memory device is different from a second time period from when the second read instruction is outputted to the memory device until data read by executing the second read method becomes ready to be transferred from the memory device.

16 . The memory system according to claim 14 , wherein
the memory device takes a first time period to complete the first read method, and the memory device takes a second time period to complete the second read method, the second time period being different from the first time period.

17 . The memory system according to claim 12 , wherein
the read instruction includes a first part indicating the one of the plurality of read methods, a second part indicating the physical address including a row address and a column address, and at least the first part is based on the physical address

Assignees

• Kioxia Corp

Inventors

• Kojima Yoshihisa

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3495

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title

• G11C2211/5648

  Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant · CPC title