Memory device

Patent metadata

Field	Value
Publication number	US-12597465-B2
Application number	US-202418585056-A
Country	US
Kind code	B2
Filing date	Feb 23, 2024
Priority date	Feb 24, 2023
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A memory device is provided. The memory device includes: a latch circuit, having a first inverter and a second inverter cross-coupled with each other, wherein a first pull up transistor and a first pull down transistor of the first inverter are coupled through a first selection transistor, and a second pull up transistor and a second pull down transistor of the second inverter are coupled through a second selection transistor; a first access transistor, coupled to a first storage node of the latch circuit; and a second access transistor, coupled to a second storage node of the latch circuit.

First claim

What is claimed is:

1 . A memory device, comprising:
a latch circuit, comprising a first inverter and a second inverter cross-coupled with each other, wherein a first pull up transistor and a first pull down transistor of the first inverter are coupled through a first selection transistor, and a second pull up transistor and a second pull down transistor of the second inverter are coupled through a second selection transistor; a first access transistor, coupled to a first storage node of the latch circuit; and a second access transistor, coupled to a second storage node of the latch circuit, wherein the first access transistor is coupled to a first bit line, the second access transistor is coupled to a second bit line, a gate terminal of the first selection transistor is controlled by a first mask bit line, and a gate terminal of the second selection transistor is controlled by a second mask bit line.

2 . The memory device according to claim 1 , wherein the first storage node is selectively coupled to the first pull up transistor through the first selection transistor, and the second storage node is selectively coupled to the second pull up transistor through the second selection transistor.

3 . The memory device according to claim 2 , wherein the first pull up transistor, the first selection transistor, the second pull up transistor and the second selection transistor are implemented by p-type transistors.

4 . The memory device according to claim 1 , wherein the first storage node is selectively coupled to the first pull down transistor through the first selection transistor, and the second storage node is selectively coupled to the second pull down transistor through the second selection transistor.

5 . The memory device according to claim 4 , wherein the first pull down transistor, the first selection transistor, the second pull down transistor and the second selection transistor are implemented by n-type transistors.

6 . The memory device according to claim 1 , wherein one of the first and second selection transistors is configured to be switched off during a write operation.

7 . The memory device according to claim 6 , wherein the one of the first and second selection transistors is configured to remain off until end of the write operation.

8 . The memory device according to claim 6 , wherein the one of the first and second selection transistors is configured to be switched on before end of the write operation.

9 . The memory device according to claim 8 , wherein the one of the first and second selection transistors is configured to be kept off until data stored at one of the first and second storage nodes is flipped during the write operation.

10 . The memory device according to claim 1 , wherein the first and second selection transistors are configured to be temporarily switched off in a standby mode of the memory device.

11 . The memory device according to claim 1 , wherein
the first mask bit line is pulled in an entire time period of a write operation, and the second mask bit line is remained at a logic low voltage during the write operation.

12 . A memory device, comprising:
a latch circuit, comprising a first inverter with a first pull up transistor, a first pull down transistor and a first selection transistor connected in between, and comprising a second inverter with a second pull up transistor, a second pull down transistor and a second selection transistor connected in between; a first access transistor, coupled to a first common source/drain terminal shared by the first selection transistor and one of the first pull up transistor and the first pull down transistor; and a second access transistor, coupled to a second common source/drain terminal shared by the second selection transistor and one of the second pull up transistor and the second pull down transistor, wherein the first access transistor is coupled to a first bit line, the second access transistor is coupled to a second bit line, a gate terminal of the first selection transistor is controlled by a first mask bit line, and a gate terminal of the second selection transistor is controlled by a second mask bit line.

13 . The memory device according to claim 12 , wherein a width/length ratio of the first and second access transistors is less than a width/length ratio of the first and second pull up transistors.

14 . The memory device according to claim 12 , wherein a beta ratio defined as a ratio of a width/length ratio of the first and second pull down transistors over a width/length ratio of the first and second access transistors is no less than 1.6.

15 . The memory device according to claim 12 , wherein a width/length ratio of first and second pull down transistors in the latch circuit is less than a width/length ratio of the first and second pull up transistors.

16 . The memory device according to claim 12 , wherein the first and second selection transistors are implemented by p-type transistors, the first access transistor is coupled to the first common source/drain terminal shared by the first selection transistor and the first pull down transistor, and the second access transistor is coupled to the second common source/drain terminal shared by the second selection transistor and the second pull down transistor.

17 . The memory device according to claim 16 , wherein the first pull up transistor and the first selection transistor are formed along a first active region, and the second pull up transistor and the second selection transistor are formed along a second active region.

18 . The memory device according to claim 12 , wherein the first and second selection transistors are implemented by n-type transistors, the first access transistor is coupled to the first common source/drain terminal shared by the first selection transistor and the first pull up transistor, and the second access transistor is coupled to the second common source/drain terminal shared by the second selection transistor and the second pull up transistor.

Assignees

• Etron Tech Inc

Inventors

• Shiah Chun
• Chen Tzung-Shen

Classifications

• H10B10/12

  comprising a MOSFET load element · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C7/106

  Data output latches · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title