Subscription to sync zones

Patent metadata

Field	Value
Publication number	US-12596595-B2
Application number	US-202217811684-A
Country	US
Kind code	B2
Filing date	Jul 11, 2022
Priority date	Jul 14, 2021
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A set of configurable sync groupings (which may be referred to as sync zones) are defined. Any of the processors may belong to any of the sync zones. Each of the processor comprises a register indicating to which of the sync zones it belongs. If a processor does not belong to a sync zone, it continually asserts a sync request for that sync zone to the sync controller. If a processor does belong to a sync zone, it will only assert its sync request for that sync zone upon arriving at a synchronisation point for that sync zone indicated in its compiled code set.

First claim

The invention claimed is:

1 . A data processing device comprising:
a plurality of processors; and a sync controller comprising circuitry configured to receive requests from the plurality of processors to participate in synchronisations and, in response to receiving the requests, return acknowledgments to the processors,
wherein each of the plurality of processors comprises:
an execution unit configured to execute a set of computer readable instructions held in memory of the respective processor; and
a register storing, for each of a set of configurable sync groups, an indication as to whether or not the respective processor belongs to the respective configurable sync group,

wherein for a first processor of the plurality of processors:
 a first indication for a first configurable sync group of the set of configurable sync groups indicates that the first processor of the plurality of processors does not belong to the first configurable sync group of the set of configurable sync groups; and
 a second indication for a second configurable sync group of the se of configurable sync groups indicates that the first processor of the plurality of processors does belong to the second configurable sync group of the set of configurable sync groups,
wherein the first processor of the plurality of processors comprises circuitry configured to, in response to the first indication for the first configurable sync group of the set of configurable sync groups indicating that the first processor of the plurality of processors does not belong to the first configurable sync group of the set of configurable sync groups, assert a first request to the sync controller to participate in a synchronisation for the first configurable sync group of the set of configurable sync groups,
wherein the circuitry of the first processor of the plurality of processors is configured to, in response to the execution unit of the first processor of the plurality of processors reaching a synchronisation point for the second configurable sync group of the set of configurable sync groups indicated in the set of computer readable instructions for the first processor of the plurality of processors, assert a second request to the sync controller to participate in a synchronisation for the second configurable sync group of the set of configurable sync groups,
further comprising aggregation circuitry configured to:
in response to each of the plurality of processors providing the first request to participate in the synchronisation for the first configurable sync group, provide a first aggregate sync request to the sync controller; and
in response to each of the plurality of processors providing the second request to participate in the synchronisation for the second configurable sync group, provide a second aggregate sync request to the sync controller,

wherein the circuitry of the sync controller is configured to return acknowledgments to the plurality of processors in response to each of the first aggregate sync request and the second aggregate sync request.

2 . The data processing device of claim 1 , wherein the circuitry of the sync controller is configured to, in response to each of the plurality of processors of the data processing device issuing the first request to participate in the synchronisation for the first configurable sync group of the set of configurable sync groups, issuing a corresponding acknowledgment to each of the plurality of processors.

3 . The data processing device of claim 2 , wherein the circuitry of the sync controller is configured to:
in response to the first requests to participate in the synchronisation for the first configurable sync group of the set of configurable sync groups, issue a further request to an external sync controller for the plurality of processors to synchronise with further processors belonging to further devices external to the data processing device; and subsequently, in response to receipt of a further acknowledgment of the further request from the external sync controller, return to each of the plurality of processors, the corresponding acknowledgment to each of the plurality of processors.

4 . The data processing device of claim 3 , comprising the external sync controller, wherein the external sync controller comprises:
storage storing a set of configuration settings for the first configurable sync group of the set of configurable sync groups; and circuitry configured to:
in response to the further request received from the sync controller, exchange one or more additional requests and one or more additional acknowledgments with the further processors belonging to further devices in dependence upon the configuration settings for the first configurable sync group of the set of configurable sync groups.

5 . The data processing device of claim 1 , wherein for each of the processors belonging to the first configurable sync group of the set of configurable sync groups, the execution unit of the respective processor is configured to, upon reaching a first barrier synchronisation enforced between the processors belonging to the first configurable sync group of the set of configurable sync groups, issue the first request to participate in the synchronisation for the first configurable sync group of the set of configurable sync groups,
wherein for the first processor of the plurality of processors, the respective execution unit is configured to, whilst the execution units of each of the processors belonging to the first configurable sync group of the set of configurable sync groups are paused waiting at the first barrier synchronisation, proceed with computation or data exchange without waiting at the first barrier synchronisation.

6 . The data processing device of claim 5 , wherein the synchronisation for the second configurable sync group of the set of configurable sync groups is a second barrier synchronisation, wherein the execution unit of the first processor of the plurality of processors is configured to:
in response to receipt of an acknowledgment to the second request to participate in the synchronisation for the second configurable sync group of the set of configurable sync groups, proceed past the second barrier synchronisation.

7 . The data processing device of claim 6 , wherein the execution unit of the first processor of the plurality of processors is configured to: proceed past the second barrier synchronisation by entering an exchange phase in which the first processor of the plurality of processors at least one of: sends or receives data.

8 . The data processing device of claim 1 , wherein the execution unit of the first processor of the plurality of processors is configured to, following assertion of the first request to participate in the synchronisation for the first configurable sync of the set of configurable sync groups, execute an update instruction to update the first indication for the first configurable sync group of the set of configurable sync groups to specify that the first processor of the plurality of processors does belong to the first configurable sync group of the set of configurable sync groups.

9 . The data processing device of claim 1 , wherein the execution unit of the first processor of the plurality of processors is configured to, following assertion of the second request to participate in the synchronisation for the second configurable sync group of the set of configurable sync groups, execute an update instruction to update the second indication for the second configurable sync group of the set of configurable sync groups to specify that the first processor of the plurality of processors does not belong to the second configurable sync group of the set of c

Assignees

• Graphcore Ltd

Inventors

• Felix Stephen
• Osborne Richard

Classifications

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title

• G06F9/522 Primary

  Barrier synchronisation · CPC title

• G06N3/063

  using electronic means · CPC title

• G06F15/1735

  Network adapters, e.g. SCI, Myrinet (protocol engines H04L69/12) · CPC title