Dual-mode floating point processor operation

Patent metadata

Field	Value
Publication number	US-12596550-B2
Application number	US-202318155834-A
Country	US
Kind code	B2
Filing date	Jan 18, 2023
Priority date	Feb 3, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

By providing a mode indication, an execution unit is operable to operate in two separate modes, each of which cause the execution unit to perform calculations by interpreting the same bit string (the first of the bit strings) as representing one of two different values. When operating in the first mode, the first of the bit string represents an undefined value, in other words a NaN. When operating in the second mode, the first of the bit strings represents a negative zero. Hence, the same string of bits can represent either a NaN or a negative zero depending upon the mode of operation of the processor. Since it is not necessary to reserve more than one bit string to represent these two special values, the remaining combinations of bits are available to represent other values.

First claim

The invention claimed is:

1 . A processing device configured to interleave execution of a plurality of threads, the processing device comprising:
an execution unit configured to execute instructions to perform operations, wherein the execution unit is configured to take at least one of a set of floating-point values as an input and produce as a result, at least one of the set of floating-point values as an output, wherein each of the set of floating-point values is represented by a respective one of a plurality of bit strings, each of the plurality of bit strings having a predefined length and provided according to a first floating-point format, a plurality of registers comprising a plurality of floating-point control registers and a plurality of status registers, wherein each of the plurality of floating-point control registers is associated with a corresponding one of the plurality of threads, wherein the plurality of floating-point control registers is configured to store a plurality of mode indications, wherein each of the plurality of mode indications indicates whether one of the operations performed by its associated thread are performed in a first mode or a second mode, wherein each of the plurality of status registers is associated with a corresponding one of the plurality of threads, wherein the execution unit is further configured to, for each of the plurality of threads:
read the mode indication stored in an associated floating-point control register of the plurality of floating-point control registers;
perform a first of the operations, and in response to the mode indication indicating operation in the first mode:
determine a result of the first of the operations in dependence upon interpreting a first of the bit strings as representing an undefined value;
raise an exception by setting an invalid operation flag in response to performing the first of the operations; and
store the invalid operation flag in an associated status register from the plurality of status registers; and

perform a second of the operations, and in response to the mode indication indicating operation in the second mode, determine a result of the second of the operations in dependence upon interpreting the first of the bit strings as representing a negative zero.

2 . The processing device of claim 1 , wherein the execution unit is configured to:
perform the first of the operations by using the first of the bit strings as an input value for the first of the operations.

3 . The processing device of claim 1 , wherein the execution unit is further configured to:
perform the second of the operations using the first of the bit strings as an input value for the second of the operations.

4 . The processing device of claim 1 , wherein the execution unit is further configured to:
output the first of the bit strings as the result of the first of the operations in response to determining that the mode indication indicates operation in the first mode.

5 . The processing device of claim 4 , wherein the first of the operations has an unrepresentable result that is too large in magnitude to be represented in the first floating-point format.

6 . The processing device of claim 4 , wherein the execution unit is further configured to subsequently perform a further instance of the first of the operations, wherein the execution unit is configured to:
in response to determining that the mode indication indicates operation in the second mode, output a further bit string, which is different to the first of the bit strings, as a result of the further instance of the first of the operations.

7 . The processing device of claim 1 , wherein the execution unit is further configured to:
output the first of the bit strings as an output value of the second of the operations in response to determining that the mode indication indicates operation in the second mode.

8 . The processing device of claim 7 , wherein the execution unit is further configured to subsequently perform a further instance of the second of the operations, wherein the execution unit is configured to:
output a further bit string, which is different to the first of the bit strings, as result of the further instance of the second of the operations and in response to determining that the mode indication indicates operation in the first mode.

9 . The processing device of claim 1 , wherein the predefined length is fewer than 16 bits.

10 . The processing device of claim 9 , wherein the predefined length is 8 bits.

11 . The processing device of claim 1 , wherein the execution unit is further configured to:
perform a third of the operations by interpreting a second bit string as representing unsigned zero in response to the mode indication indicating the first mode; and perform a fourth of the operations by interpreting the second bit string as representing positive zero in response to the mode indication indicating the second mode.

12 . The processing device of claim 1 , wherein the mode indication applies for the first floating-point format, but not for a second floating-point format.

13 . The processing device of claim 1 , wherein the execution unit is further configured to, when performing the operations:
interpret a second of the bit strings as representing a zero; and interpret each remaining possible bit sequence, other than the first of the bit strings and the second of the bit strings, that is provided according to the first floating-point format, as representing a non-zero real number.

14 . A method of interleaving execution of a plurality of threads in a processing device comprising a plurality of floating-point control registers and a plurality of status registers, the method comprising:
storing a plurality of mode indications, in the plurality of floating-point control registers, wherein each of the plurality of mode indications indicates whether an associated thread of the plurality of threads operates according to a first mode or a second mode; executing instructions to perform operations, wherein each of the operations takes a floating-point input represented by a bit string of a plurality of bit strings and produces, as a result, a floating-point output represented by another bit string of the plurality of bit strings, wherein each bit string of the plurality of bit strings has a predefined length and conforms to a first floating-point format; for a first of the plurality of threads:
reading a first mode indication from an associated floating-point control register of the plurality of floating-point control registers;
performing a first of the operations in the first mode indicated by the first mode indication, comprising:
determining a result of the first of the operations in dependence upon interpreting a first of the bit strings as representing an undefined value;
raising an exception by setting an invalid operation flag in response to performing the first of the operations; and
storing the invalid operation flag in an associated status register from the plurality of status registers; and

for a second of the plurality of threads:
reading a second mode indication from an associated floating-point control register of the plurality of floating-point control registers;
performing a second of the operations in the second mode indicated by the second mode indication, comprising determining a result of the second of the operations in dependence upon interpreting the first of the bit strings as representing a negative zero.

15 . The method of claim 14 , wherein performing the first of the operations includes using th

Assignees

• Graphcore Ltd

Inventors

• Alexander Alan

Classifications

• G06F7/49905 Primary

  Exception handling · CPC title

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3865

  using deferred exception handling, e.g. exception flags · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title