Thin film transistor, manufacturing method thereof, array substrate and display panel

Patent metadata

Field	Value
Publication number	US-12593473-B2
Application number	US-202117919301-A
Country	US
Kind code	B2
Filing date	Nov 29, 2021
Priority date	Nov 29, 2021
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

The present disclosure provides a thin film transistor, a method for manufacturing the thin film transistor, an array substrate and a display panel. The thin film transistor includes: a substrate; and a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode on the substrate, wherein the active layer includes a first semiconductor layer and a second semiconductor layer sequentially arranged in a direction perpendicular to the substrate, the second semiconductor layer is arranged on a side of the first semiconductor layer away from the gate electrode; an absolute value of a difference between conduction band minimums of a first oxide material and a second oxide material is greater than 0.2 eV.

First claim

What is claimed is:

1 . A thin film transistor, comprising:
a substrate; and a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode on the substrate, wherein the active layer comprises a first semiconductor layer and a second semiconductor layer sequentially arranged in a direction perpendicular to the substrate, the second semiconductor layer is arranged on a side of the first semiconductor layer away from the gate electrode; the first semiconductor layer comprises a first oxide material, and the second semiconductor layer comprises a second oxide material; the first oxide material has an electron mobility higher than that of the second oxide material; and the first oxide material has a conduction band minimum lower than that of the second oxide material, and an absolute value of a difference between the conduction band minimum of the first oxide material and the conduction band minimum of the second oxide material is greater than 0.2 eV, wherein the active layer further comprises a third semiconductor layer on a side of the second semiconductor layer away from the gate electrode; the third semiconductor layer comprises a crystalline oxide material; an absolute value of a conduction band minimum of the crystalline oxide material is greater than that of the conduction band minimum of the second oxide material; and the crystalline oxide material comprises crystalline IGZO (136) with an atomic ratio of In:Ga:Zn being 1:3:6 to improve physical blocking characteristics for preventing H and O elements in its adjacent layer from affecting the active layer.

2 . The thin film transistor of claim 1 , wherein
the active layer further comprises a fourth semiconductor layer on a side of the first semiconductor layer close to the gate electrode; the fourth semiconductor layer comprises a fourth oxide material; and the fourth oxide material has an electron mobility less than that of the first oxide material.

3 . The thin film transistor of claim 2 , wherein
the fourth oxide material and the second oxide material are a same material.

4 . The thin film transistor of claim 3 , wherein
the first oxide material comprises at least one of IGZO, IZO, IGTO, ITZO, and IGZTO; and the second oxide material comprises at least one of GZO and Pr-GZO, where Pr-GZO is GZO doped with praseodymium element, and GZO is GZO (73) with an atomic ratio of Ga:Zn being 7:3 or GZO (37) with an atomic ratio of Ga:Zn being 3:7.

5 . The thin film transistor of claim 4 , wherein
the gate insulating layer is on a side of the gate electrode away from the substrate; the active layer is on a side of the gate insulating layer away from the substrate; areas of orthographic projections of the first semiconductor layer and the second semiconductor layer on the substrate are substantially the same; and the source electrode and the drain electrode are in contact with two opposite ends of each of the first semiconductor layer and the second semiconductor layer on the gate insulating layer, respectively.

6 . The thin film transistor of claim 4 , further comprising a buffer layer and an interlayer dielectric layer on the substrate, wherein
the second semiconductor layer is on a side of the buffer layer away from the substrate; the first semiconductor layer is on a side of the second semiconductor layer away from the substrate; the gate insulating layer is on a side of the first semiconductor layer away from the substrate; the gate electrode is on a side of the gate insulating layer away from the substrate; the interlayer dielectric layer is on a side of the gate electrode away from the substrate; areas of orthographic projections of the first semiconductor layer and the second semiconductor layer on the substrate are substantially the same; and the source electrode and the drain electrode are in contact with two opposite ends of the first semiconductor layer through a first via and a second via in the interlayer dielectric layer, respectively.

7 . An array substrate, comprising a light emitting device and a driving circuit for driving the light emitting device to emit light, wherein the driving circuit comprises the thin film transistor of claim 1 .

8 . A display panel, comprising the array substrate of claim 7 .

9 . The thin film transistor of claim 1 , wherein
the first oxide material comprises at least one of IGZO, IZO, IGTO, ITZO, and IGZTO; and the second oxide material comprises at least one of GZO and Pr-GZO, where Pr-GZO is GZO doped with praseodymium element, and GZO is GZO (73) with an atomic ratio of Ga:Zn being 7:3 or GZO (37) with an atomic ratio of Ga:Zn being 3:7.

10 . A method for manufacturing a thin film transistor, comprising:
forming a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode on a substrate, wherein the active layer comprises a first semiconductor layer and a second semiconductor layer sequentially arranged in a direction perpendicular to the substrate, the second semiconductor layer is arranged on a side of the first semiconductor layer away from the gate electrode; the first semiconductor layer comprises a first oxide material, and the second semiconductor layer comprises a second oxide material; the first oxide material has an electron mobility higher than that of the second oxide material; and the first oxide material has a conduction band minimum lower than that of the second oxide material, and an absolute value of a difference between the conduction band minimum of the first oxide material and the conduction band minimum of the second oxide material is greater than 0.2 eV, wherein the active layer further comprises a third semiconductor layer on a side of the second semiconductor layer away from the gate electrode; the third semiconductor layer comprises a crystalline oxide material; and an absolute value of a conduction band minimum of the crystalline oxide material is greater than that of the conduction band minimum of the second oxide material; and the crystalline oxide material comprises crystalline IGZO (136) with an atomic ratio of In:Ga:Zn being 1:3:6 to improve physical blocking characteristics for preventing H and O elements in its adjacent layer from affecting the active layer.

11 . The method of claim 10 , wherein
the first oxide material comprises at least one of IGZO, ITZO, IZO, IGTO, and IGZTO; and the second oxide material comprises at least one of GZO and Pr-GZO, where Pr-GZO is GZO doped with praseodymium element, and GZO is GZO (73) with an atomic ratio of Ga:Zn being 7:3 or GZO (37) with an atomic ratio of Ga:Zn being 3:7.

12 . The method of claim 11 , wherein the forming a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode on a substrate, comprises:
forming a pattern of the gate electrode on the substrate; forming the gate insulating layer on the pattern of the gate electrode; sequentially forming a first oxide material layer and a second oxide material layer on the gate insulating layer, and forming patterns of the first semiconductor layer and the second semiconductor layer on the gate insulating layer by one patterning process with a first mask; forming a source-drain material layer on the patterns of the first semiconductor layer and the second semiconductor layer on the gate insulating layer, and etching the source-drain material layer to form the source electrode and the drain electrode at two opposite ends of the first semiconductor layer, respectively; and forming a passivation layer on the source electrode and the drain electrode.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Huang Jie
• Ning ce
• Li Zhengliang
• Hu hehe
• He Jiayu
• Yao Nianqi
• Zhao Kun
• Li Feifei
• Lei Liping

Classifications

• H10D99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10P10/00

  Bonding of wafers, substrates or parts of devices · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title