Integrated circuit

Patent metadata

Field	Value
Publication number	US-12592694-B2
Application number	US-202418598655-A
Country	US
Kind code	B2
Filing date	Mar 7, 2024
Priority date	May 11, 2023
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

An integrated circuit includes a Wheatstone bridge and a bias voltage circuit. The Wheatstone bridge includes a first resistor connected between a first node on a high potential side at which a predetermined voltage is generated and a second node, a second resistor connected between the second node and a third node on a low potential side, a third resistor connected between the first node and a fourth node, and a fourth resistor connected between the fourth node and the third node. The bias voltage circuit includes a fifth resistor having a first end connected to the third node and a second end, and a first operational amplifier circuit having an inverting input terminal to which the second end of the fifth resistor is connected, a non-inverting input terminal configured to receive a reference voltage lower than the predetermined voltage, and an output terminal connected to the third node.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a Wheatstone bridge having
a first node on a high potential side thereof,
a second node,
a third node on a low potential side thereof, the first node having a higher potential than the third node, and
a fourth node,

the Wheatstone bridge including:
a first resistor connected between the first node and the second node,
a second resistor connected between the second node and the third node,
a third resistor connected between the first node and the fourth node, and
a fourth resistor connected between the fourth node and the third node,

the Wheatstone bridge being configured to have a predetermined voltage at the first node; and
a bias voltage circuit, including
a fifth resistor having
a first end connected to the third node, and
a second end; and

a first operational amplifier circuit having
an inverting input terminal to which the second end of the fifth resistor is connected,
a non-inverting input terminal configured to receive a reference voltage lower than the predetermined voltage, and
an output terminal connected to the third node.

2 . The integrated circuit according to claim 1 , wherein the first resistor, the second resistor, the third resistor, the fourth resistor, and the fifth resistor are of a same type.

3 . The integrated circuit according to claim 2 , wherein a resistance value of each of the first resistor, the second resistor, the third resistor, and the fourth resistor is equal to a resistance value of the fifth resistor.

4 . The integrated circuit according to claim 1 , wherein the bias voltage circuit further includes a second operational amplifier circuit having
a non-inverting input terminal configured to receive the predetermined voltage, an inverting input terminal connected to the first node, and an output terminal connected to the third node.

5 . The integrated circuit according to claim 4 , wherein the bias voltage circuit further includes a sixth resistor having
a first end configured to receive a power supply voltage, and a second end connected to the first node.

6 . The integrated circuit according to claim 5 , wherein the first resistor, the second resistor, the third resistor, the fourth resistor, the sixth resistor are of a same type.

7 . The integrated circuit according to claim 5 , wherein the bias voltage circuit further includes a bias current circuit through which part of a current flowing through the sixth resistor flows.

8 . The integrated circuit according to claim 1 , wherein the bias voltage circuit further includes a reference voltage circuit configured to adjust a level of the reference voltage and output a resultant reference voltage.

Assignees

• Fuji Electric Co Ltd

Inventors

• Ito Yuichi

Classifications

• G01L9/04

  of resistance-strain gauges · CPC title

• H03K17/56 Primary

  by the use, as active elements, of semiconductor devices (using diodes H03K17/74) · CPC title