Electronic circuit and method

Patent metadata

Field	Value
Publication number	US-12592686-B2
Application number	US-202418830200-A
Country	US
Kind code	B2
Filing date	Sep 10, 2024
Priority date	Oct 10, 2023
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

The present description relates to an electronic circuit comprising a first circuit configured to generate, based on a first periodic analog signal, a plurality of second signals having offset voltage levels, a second circuit configured to generate third periodic digital signals according to respective crossings, by the second signals, of at least one threshold, and a third circuit configured to determine an amplitude range in which the first periodic analog signal is located, according to a number of the third periodic digital signals.

First claim

The invention claimed is:

1 . An electronic circuit comprising:
a first circuit configured to generate, based on a first periodic analog signal, a plurality of second signals having voltage levels offset from each other; a second circuit configured to generate third periodic digital signals according to respective crossings, by the second signals, of at least one threshold; and a third circuit configured to determine an amplitude range in which the first periodic analog signal is located, according to a number of the third periodic digital signals.

2 . The electronic circuit according to claim 1 , wherein the second circuit is configured to generate each third periodic digital signal in response to a corresponding one of the second signals crossing two thresholds.

3 . The electronic circuit according to claim 1 , wherein the electronic circuit comprises a fourth circuit configured to adjust an amplitude of the first periodic analog signal according to the determined amplitude range.

4 . The electronic circuit according to claim 3 , wherein the third circuit comprises three branches, wherein each branch comprises a plurality of flip-flops in series, and wherein each branch is configured to respectively receive one of the third periodic digital signals on a clock input of the flip-flops of the respective branch.

5 . The electronic circuit according to claim 4 , wherein each branch comprises at least two D-type flip-flops in a series of flip-flops.

6 . The electronic circuit according to claim 5 , wherein the third circuit comprises a first logic block configured to perform an AND function based on an output of the series of flip-flops of a first branch from among the branches and based on an output of the series of flip-flops of a second branch from among the branches.

7 . The electronic circuit according to claim 6 , wherein the third circuit comprises a second logic block configured to perform an AND function based on the output of the series of flip-flops of the second branch and based on an output of the series of flip-flops of a third branch from among the branches.

8 . The electronic circuit according to claim 7 , wherein the third circuit is configured to generate a first pulse on a first path in response to outputs of the first and second branches having a high logic state.

9 . The electronic circuit according to claim 8 , wherein the third circuit is configured to generate a second pulse on a second path in response to the output of the second branch and an output of the third branch having the high logic state.

10 . The electronic circuit according to claim 6 , wherein the third circuit is configured to generate pulses on first and second paths in response to a signal at an output of the second branch having a high logic state.

11 . The electronic circuit according to claim 10 , wherein the fourth circuit is configured to generate a control signal modifying the amplitude of the first periodic analog signal according to a presence or an absence of the pulses on the first and second paths.

12 . The electronic circuit according to claim 2 , wherein each third periodic digital signal is generated by a respective voltage comparator having the two thresholds as trigger thresholds.

13 . The electronic circuit according to claim 12 , wherein each voltage comparator is of Schmitt trigger type.

14 . The electronic circuit according to claim 12 , wherein each voltage comparator has an input node coupled to a first node configured to receive the first periodic analog signal, via a respective capacitive element, and wherein each input node of each comparator is configured to respectively receive one of the second signals.

15 . The electronic circuit according to claim 14 , wherein the first circuit comprises resistors in series between a power supply node configured to receive a power supply voltage and ground, each of the second signals being generated based on a voltage present on a different node corresponding to a junction point of two adjacent resistors of the resistors in series.

16 . The electronic circuit according to claim 15 , wherein the first circuit comprises a p-channel metal oxide semiconductor (PMOS) transistor and an n-channel metal oxide semiconductor (NMOS) transistor, each having a conduction node connected to a reference node, control nodes of the PMOS and NMOS transistors being connected to the reference node, another conduction node of the PMOS transistor being connected to the power supply node, and another conduction node of the NMOS transistor being connected to the ground.

17 . The electronic circuit according to claim 16 , wherein the reference node is coupled to the ground via one of the resistors of the resistors in series.

18 . The electronic circuit according to claim 17 , wherein each comparator comprises a dual inverter circuit coupling the power supply node and the ground;
wherein the dual inverter circuit comprises two PMOS transistors and two NMOS transistors in series; and wherein a control node, common to the PMOS and NMOS transistors of the dual inverter circuit, is coupled to the reference node.

19 . The electronic circuit according to claim 1 , wherein the first periodic analog signal originates from a crystal oscillator.

20 . A near-field communication (NFC) microcontroller comprising:
a processor; and an electronic circuit, communicatively coupled to the processor, comprising:
a first circuit configured to generate, based on a first periodic analog signal, a plurality of second signals having voltage levels offset from each other;
a second circuit configured to generate third periodic digital signals according to respective crossings, by the second signals, of at least one threshold; and
a third circuit configured to determine an amplitude range in which the first periodic analog signal is located, according to a number of the third periodic digital signals.

21 . A method of operating an electronic circuit, the method comprising:
generating, with a first circuit of the electronic circuit, based on a first periodic analog signal, a plurality of second signals having voltage levels offset from each other; generating, with a second circuit of the electronic circuit, third periodic digital signals according to respective crossings, by the second signals, of at least one threshold; and determining, with a third circuit of the electronic circuit, an amplitude range in which the first periodic analog signal is located, according to a number of the third periodic digital signals.

22 . The method according to claim 21 , further comprising generating, by the second circuit, each third periodic digital signal in response to a corresponding one of the second signals crossing two thresholds.

23 . The method according to claim 21 , further comprising adjusting, by a fourth circuit of the electronic circuit, an amplitude of the first periodic analog signal according to the determined amplitude range.

24 . The method according to claim 21 , wherein the third circuit comprises three branches, each branch comprising a plurality of flip-flops in a series of flip-flops, and the method further comprises:
receiving, respectively by each branch, one of the third periodic digital signals on a clock input of the flip-flops of the respective branch.

25 . The method according to claim 24 , wherein each branch comprises at least two D-type flip-flop

Assignees

• St Microelectronics Int Nv
• Stmicroelectronics France

Inventors

• Razafimandimby Stephane

Classifications

• H03K5/24

  the characteristic being amplitude · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H04B5/73

  for taking measurements, e.g. using sensing coils · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R19/16528

  using digital techniques or performing arithmetic operations (using digital techniques to measure a voltage or a current, see G01R19/25) · CPC title