Non-volatile memory with in-place error updating and correction

Patent metadata

Field	Value
Publication number	US-12592291-B2
Application number	US-202418419205-A
Country	US
Kind code	B2
Filing date	Jan 22, 2024
Priority date	Jan 22, 2024
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A non-volatile memory attempts to read a data set from a plurality of non-volatile memory cells in multiple threshold voltages distributions and determines that the data set was not read successfully due to there being too many errors in the data read. In response to determining that the data set was not read successfully, the system identifies memory cells storing error bits that are in upper tails and lower tails of the threshold voltages distributions. To reduce the number of errors, memory cells storing error bits that are in upper tails have their threshold voltages reduced by bit level erase and memory cells storing error bits that are in lower tails their threshold voltages increased to move the memory cells closer to the center of their respective threshold voltages distributions by bit level program.

First claim

What is claimed is:

1 . A non-volatile storage apparatus, comprising:
non-volatile memory cells arranged in NAND strings, each of the NAND string including a Gate Induced Drain Leakage (“GIDL”) transistor; and a control circuit connected to the non-volatile memory cells, the control circuit is configured to:
identify first memory cells in an upper tail of a threshold voltage distribution for a first data state, and
lower threshold voltages of the identified first memory cells to be at lower threshold voltages within the threshold voltage distribution for the first data state without lowering the threshold voltages of the identified first memory cells to be lower than the threshold voltage distribution for the first data state by:
causing a positive drain-to-gate voltage at GIDL generation transistors in NAND strings that include the identified first memory cells by applying an erase voltage to bit lines connected to the NAND strings that include the identified first memory cells and applying a GIDL generation voltage to the GIDL generation transistors in NAND strings that include the identified first memory cells, the GIDL generation voltage is lower than the erase voltage, and
causing a negative drain-to-gate voltage at GIDL generation transistors in NAND strings that do not include the identified first memory cells by applying an erase inhibit voltage to bit lines connected to NAND strings that do not include the identified first memory cells and applying a GIDL inhibit voltage to the GIDL generation transistors in NAND strings that do not include the identified first memory cells, the GIDL inhibit voltage is higher than the erase inhibit voltage, the erase inhibit voltage is lower than the erase voltage.

2 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to read a data set from the non-volatile memory cells and determine that the data set was not read successfully; and the control circuit is configured to identify memory cells in the upper tail and lower threshold voltages in response to determining that the data set was not read successfully.

3 . The non-volatile storage apparatus of claim 2 , wherein:
the control circuit is configured to identify first memory cells in the upper tail of the threshold voltage distribution for the first data state by identifying memory cells storing error bits for the data set and determining which of the memory cells identified to be storing error bits for the data set have threshold voltages in the upper tail of the threshold voltage distribution for the first data state.

4 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to lower threshold voltages by lowering threshold voltages of the identified first memory cells to be at lower threshold voltages within the threshold voltage distribution for the first data state without concurrently lowering the threshold voltages of other memory cells.

5 . The non-volatile storage apparatus of claim 1 , wherein the control circuit is further configured to:
identify second memory cells in a lower tail of a threshold voltage distribution for a second data state, and raise threshold voltages of the identified second memory cells to be at higher threshold voltages within the threshold voltage distribution for the second data state without lowering the threshold voltages of the identified second memory cells to be lower than the threshold voltage distribution for the second data state.

6 . The non-volatile storage apparatus of claim 5 , wherein:
the threshold voltage distribution for the second data state overlaps with the threshold voltage distribution for the first data state; and a center of the threshold voltage distribution for the second data state is higher in voltage magnitude than a center of the threshold voltage distribution for the first data state.

7 . The non-volatile storage apparatus of claim 5 , wherein:
the control circuit is configured to read a data set from the non-volatile memory cells and determine that the data set was not read successfully; and the control circuit is configured to identify memory cells in the upper tail, lower threshold voltages, identify memory cells in the lower tail and raise threshold voltages in response to determining that the data set was not read successfully.

8 . The non-volatile storage apparatus of claim 7 , wherein:
the control circuit is configured to identify first memory cells in the upper tail of the threshold voltage distribution for the first data state by identifying memory cells storing error bits for the data set and determining which of the memory cells identified to be storing error bits for the data set have threshold voltages in the upper tail of the threshold voltage distribution for the first data state; and the control circuit is configured to identify second memory cells in the lower tail of the threshold voltage distribution for the second data state by identifying memory cells storing error bits for the data set and determining which of the memory cells identified to be storing error bits for the data set have threshold voltages in the lower tail of the threshold voltage distribution for the second data state.

9 . The non-volatile storage apparatus of claim 5 , wherein:
the threshold voltage distribution for the first data state and the threshold voltage distribution for the second data state are part of a set of multiple overlapping threshold voltage distributions; the control circuit is configured to read a page of data from the non-volatile memory cells and determine that the page of data was not read successfully; and the control circuit is configured to identify memory cells in the upper tail of the threshold voltage distribution for the first data state and identify memory cells in the lower tail of the threshold voltage distribution for a second data state by identifying memory cells at upper tails and lower tails of a subset of neighboring threshold voltage distributions of the multiple threshold voltage distributions.

10 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to lower threshold voltages by lowering threshold voltages of the identified first memory cells to be at lower threshold voltages within the threshold voltage distribution for the first data state without raising the threshold voltages of the identified first memory cells.

11 . The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to persistently maintain the identified first memory cells in the first data state after the lowering.

12 . A method comprising:
reading a data set from a plurality of non-volatile memory cells in overlapping threshold voltages distributions, the plurality of non-volatile memory cells are arranged in NAND strings, each of the NAND string including a Gate Induced Drain Leakage (“GIDL”) transistor; determining that the data set was not read successfully; and in response to determining that the data set was not read successfully:
identifying memory cells storing error bits by identifying memory cells in threshold voltage overlap regions between neighboring overlapping threshold voltages distributions;
determining which of the identified memory cells in threshold voltage overlap regions have threshold voltages in upper tails by determining which of the identified memory cells in threshold voltage overlap regions have threshold voltages above a respective demarcation voltage within the overlap regions;
determining which of the identified memory cells in threshold voltage overlap regions have thr

Assignees

• Sandisk Technologies Inc

Inventors

• Li Liang
• Wang Ming
• Yuan Jiahui

Classifications

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title