Driving circuit, driving method, pixel circuit, display panel and display device

Patent metadata

Field	Value
Publication number	US-12592199-B2
Application number	US-202318686657-A
Country	US
Kind code	B2
Filing date	Mar 29, 2023
Priority date	Mar 29, 2023
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A driving circuit, a driving method, a pixel circuit, a display panel and a display device are provided. The driving circuit includes a first switching circuit and a scanning signal generation circuit; the first switching circuit is electrically connected to a first gating control line, at least two data output terminals of a source driver and the scanning signal generation circuit, and is configured to write a data signal provided by the at least two data output terminals into the scanning signal generation circuit under the control of a first gating control signal provided by the first gating control line; the scanning signal generation circuit is configured to generate a scanning signal according to the data signal, and output the scanning signal through the scanning signal output terminal.

First claim

What is claimed is:

1 . A driving circuit, comprising a first switching circuit and a scanning signal generation circuit; wherein
the first switching circuit is electrically connected to a first gating control line, at least two data output terminals of a source driver and the scanning signal generation circuit, and is configured to write a data signal provided by the at least two data output terminals into the scanning signal generation circuit under the control of a first gating control signal provided by the first gating control line; the scanning signal generation circuit is configured to generate a scanning signal according to the data signal, and output the scanning signal through the scanning signal output terminal; wherein the at least two data output terminals are electrically connected to different columns of data lines included in a display panel respectively; a scanning signal output terminal of the scanning signal generation circuit is electrically connected to a column of scanning line included in the display panel.

2 . The driving circuit according to claim 1 , wherein the driving circuit further comprises a second switching circuit;
the second switching circuit is electrically connected to a second gating control line, the at least two data output terminals of the source driver and at least two data lines included in a display panel respectively, and is configured to control to connect or disconnect the at least two data output terminals of the source driver and a column of data line included in the display panel respectively under the control of a second gating control signal provided by the second gating control line; the first gating control line is a same gating control line as the second gating control line, or the first gating control line is different from the second gating control line.

3 . The driving circuit according to claim 1 , wherein the first switching circuit is respectively electrically connected to the first gating control line, a (2m−1)th data output terminal of the source driver, a 2mth data output terminal of the source driver, a first control node and a second control node, is configured to control to connect or disconnect the (2m−1)th data output terminal and the first control node and control to connect or disconnect the 2mth data output terminal and the second control node under the control of the first gating control signal provided by the first gating control line;
m is a positive integer.

4 . The driving circuit according to claim 3 , wherein the first switching circuit includes a first transistor, a second transistor, a first capacitor and a second capacitor;
a gate electrode of the first transistor is electrically connected to the first gating control line, a first electrode of the first transistor is electrically connected to the (2m−1)th data output terminal, and a second electrode of the first transistor is electrically connected to the first control node; a gate electrode of the second transistor is electrically connected to the first gating control line, a first electrode of the second transistor is electrically connected to the 2mth data output terminal, and a second electrode of the second transistor is electrically connected to the second control node; a first terminal of the first capacitor is electrically connected to the first control node, and a second terminal of the first capacitor is electrically connected to a control voltage terminal; a first terminal of the second capacitor is electrically connected to the second control node, and a second terminal of the second capacitor is electrically connected to the control voltage terminal.

5 . The driving circuit according to claim 3 , wherein the scanning signal generation circuit includes an output control circuit and a first output circuit;
the output control circuit is electrically connected to the first control node, a first voltage terminal, a second voltage terminal, an output control terminal and a scanning output terminal respectively, is configured to control to connect or disconnect the output control terminal and the first voltage terminal under the control of a potential of the first control node, and control to connect or disconnect the output control terminal and the second voltage terminal under the control of a signal provided by the scanning output terminal; the first output circuit is electrically connected to the second control node, the output control terminal, the scanning output terminal, the first voltage terminal and the second voltage terminal respectively, and is configured to control to connect or disconnect the scanning output terminal and the first voltage terminal under the control of a potential of the second control node, and control to connect or disconnect the scanning output terminal and the second voltage terminal under the control of a potential of the output control terminal.

6 . The driving circuit according to claim 5 , wherein the scanning output terminal is the scanning signal output terminal; or
the scanning signal generation circuit further includes an inverting circuit; an input terminal of the inverting circuit is electrically connected to the scanning output terminal, an output terminal of the inverting circuit is electrically connected to the scanning signal output terminal, and the inverting circuit is configured to perform phase inversion on a voltage signal that is connected to the input terminal of the inverting circuit, obtains an inverted voltage signal, and outputs the inverted voltage signal through the output terminal of the inverting circuit.

7 . The driving circuit according to claim 5 , wherein the output control circuit includes a third transistor and a fourth transistor;
a gate electrode of the third transistor is electrically connected to the first control node, a first electrode of the third transistor is electrically connected to the first voltage terminal, and a second electrode of the third transistor is electrically connected to the output control terminal; a gate electrode of the fourth transistor is electrically connected to the scanning output terminal, a first electrode of the fourth transistor is electrically connected to the output control terminal, and a second electrode of the fourth transistor is electrically connected to the second voltage terminal; the output circuit includes a fifth transistor and a sixth transistor; a gate electrode of the fifth transistor is electrically connected to the second control node, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the scanning output terminal; a gate electrode of the sixth transistor is electrically connected to the output control terminal, a first electrode of the sixth transistor is electrically connected to the scanning output terminal, and a second electrode of the sixth transistor is electrically connected to the second voltage terminal.

8 . The driving circuit according to claim 3 , wherein the scanning signal generation circuit includes a first output control circuit, a second output control circuit, a third output control circuit, a fourth output control circuit and a second output circuit;
the first output control circuit is electrically connected to the first control node, a third control node and a connection node respectively, and is configured to control to connect or disconnect the third control node and the connection node under the control of the potential of the first control node; the second output control circuit is electrically connected to the second control node, a fourth control node and the connection node respectively, and is configured to control to c

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Yu Ziyang
• Qiu Haijun
• Hu Ming
• Jiang Zhiliang
• Yan Qingqing
• Gu Quanyong
• Cheng Tianyi
• Wu Jianpeng
• Zhang Tiaomei
• Chen Wenbo
• Zhao Pan
• Wei Qi
• Li Qian

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G3/3225

  using an active matrix · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title