Display panel and control method therefor, and display device

Patent metadata

Field	Value
Publication number	US-12592193-B2
Application number	US-202418851580-A
Country	US
Kind code	B2
Filing date	Jan 16, 2024
Priority date	Feb 22, 2023
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

Provided is a display panel. The display panel includes: a substrate; and a plurality of pixels on the substrate, wherein at least one of the plurality of pixels includes a plurality of sets of sub-pixels, at least one set of the plurality of sets of sub-pixels including a plurality of sub-pixels of a same color; wherein each of the plurality of sub-pixels includes: a drive circuit, coupled to a first control line, a data line, a first power line, and a first node; a compensation circuit, coupled to a second control line, a sensing line, and the first node; a light-emitting element, coupled to the first node and a second power line; and a shielding circuit, connected in series to any light-emitting channel.

First claim

The invention claimed is:

1 . A display panel, comprising:
a substrate; and a plurality of pixels on the substrate, wherein at least one of the plurality of pixels comprises a plurality of sets of sub-pixels, at least one set of the plurality of sets of sub-pixels comprising a plurality of sub-pixels of a same color; wherein each of the plurality of sub-pixels comprises:
a drive circuit, coupled to a first control line, a data line, a first power line, and a first node, and configured to control on or off between the first power line and the first node based on a first control signal supplied by the first control line and a data signal supplied by the data line and to control a potential of the first node based on the data signal and a first power signal supplied by the first power line;
a compensation circuit, coupled to a second control line, a sensing line, and the first node, and configured to control on or off between the sensing line and the first node based on a second control signal supplied by the second control line;
a light-emitting element, coupled to the first node and a second power line, and configured to emit light based on the potential of the first node and a second power signal supplied by the second power line; and
a shielding circuit, connected in series to any light-emitting channel, and configured to switch off the light-emitting channel in response to a dark spot of the light-emitting element, wherein the light-emitting channel comprises a first light-emitting channel and a second light-emitting channel, wherein the first light-emitting channel comprises a channel over which the first power line is coupled to the light-emitting element, and the second light-emitting channel comprises a channel over which the sensing line is coupled to the light-emitting element;
wherein the shielding circuit comprises a shielding resistor; and, in a direction parallel to a bearing face of the substrate, at least one terminal of the shielding resistor comprises a rib structure, wherein a recess indented towards a side of the shielding resistor in a direction perpendicular to the substrate is formed in the rib structure.

2 . The display panel according to claim 1 , wherein the drive circuit comprises:
a data write sub-circuit, coupled to the first control line, the data line, and a second node, and configured to control on or off between the data line and the second node based on the first control signal supplied by the first control line; a drive sub-circuit, coupled to the second node, the first power line, and the first node, and configured to control on or off between the first power line and the first node based on a potential of the second node and to control the potential of the first node based on the potential of the second node and the first power signal; and an adjustment sub-circuit, coupled to the second node and the first node, and configured to adjust the potential of one of the second node and the first node based on the potential of the other of the second node and the first node; wherein the first light-emitting channel further comprises the drive sub-circuit.

3 . The display panel according to claim 2 , wherein the shielding circuit is connected in series between the first power line and the drive sub-circuit.

4 . The display panel according to claim 3 , wherein the data write sub-circuit comprises: a data write transistor, the drive sub-circuit comprises a drive transistor, the adjustment sub-circuit comprises a storage capacitor, and the compensation circuit comprises a compensation transistor; wherein
a control electrode of the data write transistor is coupled to the first control line, a first electrode of the data write transistor is coupled to the data line, and a second electrode of the data write transistor is coupled to the second node; a control electrode of the drive transistor is coupled to the second node, a first electrode of the drive transistor is coupled to one terminal of the shielding circuit, the other terminal of the shielding circuit is coupled to the first power line, and a second electrode of the drive transistor is coupled to the first node; one terminal of the storage capacitor is coupled to the first node, and the other terminal of the storage capacitor is coupled to the second node; and a gate electrode of the compensation transistor is coupled to the second control line, a first electrode of the compensation transistor is coupled to the sensing line, and a second electrode of the compensation transistor is coupled to the first node.

5 . The display panel according to claim 2 , wherein the second light-emitting channel further comprises the compensation circuit, wherein the shielding circuit is connected in series between the light-emitting element and the compensation circuit.

6 . The display panel according to claim 5 , wherein the data write sub-circuit comprises: a data write transistor, the drive sub-circuit comprises a drive transistor, the adjustment sub-circuit comprises a storage capacitor, and the compensation circuit comprises a compensation transistor; wherein
a control electrode of the data write transistor is coupled to the first control line, a first electrode of the data write transistor is coupled to the data line, and a second electrode of the data write transistor is coupled to the second node; a control electrode of the drive transistor is coupled to the second node, a first electrode of the drive transistor is coupled to the first power line, and a second electrode of the drive transistor is coupled to the first node; one terminal of the storage capacitor is coupled to the first node, and the other terminal of the storage capacitor is coupled to the second node; and a control electrode of the compensation transistor is coupled to the second control line, a first electrode of the compensation transistor is coupled to the sensing line, a second electrode of the compensation transistor is coupled to one terminal of the shielding circuit, and the other terminal of the shielding circuit is coupled to the first node.

7 . The display panel according to claim 1 , wherein in the direction parallel to the bearing face of the substrate, the shielding resistor comprises a first structure and a second structure, wherein a distance between a side, away from the substrate, of the second structure and the substrate is greater than a distance between a side, away from the substrate, of the first structure and the substrate.

8 . The display panel according to claim 7 , wherein the first structure is disposed on two sides of the second structure, and is configured to connect the second structure in series to any light-emitting channel; and the first structure comprises the rib structure, and a recess indented towards a center of the first structure is formed in each of two sides of the first structure in the direction parallel to the bearing face of the substrate.

9 . The display panel according to claim 7 , wherein the first structure comprises a plurality of first film layers sequentially laminated in a direction away from the substrate, and the second structure comprises a plurality of second film layers sequentially laminated in the direction away from the substrate, wherein at least one of the plurality of first film layers and the plurality of second film layers is disposed on a same layer as a film layer in each of the plurality of sub-pixels.

10 . The display panel according to claim 9 , wherein
each of the plurality of sub-pixels comprises a gate metal layer, a source-drain metal layer, a planarization layer, an anode layer, a pixel definition layer, a light-emitting layer, and a cathode layer that are sequentially laminat

Assignees

• Hefei Boe Joint Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• He Min
• Yuan Can
• Yin Pengfei
• Cao Shuyu
• Fei Qiang

Classifications

• G09G2320/046

  Dealing with screen burn-in prevention or compensation of the effects thereof · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title