Pixel circuits and display panels

Patent metadata

Field	Value
Publication number	US-12592188-B2
Application number	US-202318254869-A
Country	US
Kind code	B2
Filing date	Apr 20, 2023
Priority date	Feb 28, 2023
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A pixel circuit includes a first light-emitting control transistor, a driving transistor, a second light-emitting control transistor, and a light-emitting device. The number of times a source or a drain of the driving transistor is reset in one frame is configured to be larger than the number of times the anode of the light-emitting device is reset in the one frame.

First claim

What is claimed is:

1 . A pixel circuit comprising:
a first light-emitting control transistor, one of a source or a drain of the first light-emitting control transistor being electrically connected to a first power supply line; a driving transistor, one of a source or a drain of the driving transistor being electrically connected to another of the source or the drain of the first light-emitting control transistor; a second light-emitting control transistor, one of a source or a drain of the second light-emitting control transistor being electrically connected to another of the source or the drain of the driving transistor; a light-emitting device, an anode of the light-emitting device being electrically connected to another of the source or the drain of the second light-emitting control transistor, and a cathode of the light-emitting device being electrically connected to a second power supply line; a first reset transistor, one of a source or a drain of the first reset transistor being electrically connected to the anode of the light-emitting device, another of the source or the drain of the first reset transistor being electrically connected to a first reset line, and a gate of the first reset transistor being electrically connected to a first control line; and a bias transistor, one of a source or a drain of the bias transistor being electrically connected to the source or the drain of the driving transistor, another of the source or the drain of the bias transistor being electrically connected to a first wiring, and a gate of the bias transistor being electrically connected to a second wiring; wherein a number of times the source or drain of the driving transistor is reset in one frame is greater than a number of times the anode of the light-emitting device is reset in the one frame; the one frame comprises at least one first period and at least one second period; during the at least one first period, both the first reset transistor and the bias transistor are turned on; and during the at least one second period, the first reset transistor is turned off, and the bias transistor is turned on; wherein in a condition that the bias transistor is a second reset transistor, the one frame comprises a writing frame and a holding frame, a number of times the second reset transistor is turned on in the writing frame is greater than a number of times the first reset transistor is turned on in the writing frame, and a number of times the second reset transistor is turned on in the holding frame is greater than a number of times the first reset transistor is turned on in the holding frame.

2 . The pixel circuit according to claim 1 , wherein the first wiring is a second reset line, and the second wiring is a second control line; one of a source or a drain of the second reset transistor is electrically connected to the source or the drain of the driving transistor, another of the source or the drain of the second reset transistor is electrically connected to the second reset line, and a gate of the second reset transistor is electrically connected to the second control line, and
wherein a number of times the second reset transistor is turned on in the one frame is greater than a number of times the first reset transistor is turned on in the one frame.

3 . The pixel circuit according to claim 2 , wherein the first control line is configured to transmit a first control signal, and the second control line is configured to transmit a second control signal, a number of pulses of the second control signal in the one frame is greater than a number of pulses of the first control signal in the one frame.

4 . The pixel circuit according to claim 3 , wherein the one frame comprises a writing frame and a holding frame, a number of pulses of the second control signal in the writing frame is greater than a number of pulses of the first control signal in the writing frame, and a number of pulses of the second control signal in the holding frame is greater than a number of pulses of the first control signal in the holding frame.

5 . The pixel circuit according to claim 1 , wherein in a condition that the bias transistor is a writing transistor, the first wiring is a data line, and the second wiring is a third control line; one of a source or a drain of the writing transistor is electrically connected to the source or the drain of the driving transistor, another of the source or the drain of the writing transistor is electrically connected to the data line, and a gate of the writing transistor is electrically connected to the third control line, and
wherein a number of times the writing transistor is turned on in the one frame is greater than a number of times the first reset transistor is turned on in the one frame.

6 . The pixel circuit according to claim 5 , wherein the one frame comprises a writing frame and a holding frame, a number of times the writing transistor is turned on in the writing frame is greater than a number of times the first reset transistor is turned on in the writing frame, and a number of times the writing transistor is turned on in the holding frame is greater than a number of times the first reset transistor is turned on in the holding frame.

7 . The pixel circuit according to claim 5 , wherein the first control line is configured to transmit a first control signal, and the third control line is configured to transmit a third control signal, a number of pulses of the third control signal in the one frame is greater than a number of pulses of the first control signal in the one frame.

8 . The pixel circuit according to claim 7 , wherein the data line is configured to transmit a data signal, the one frame comprises a writing frame and a holding frame, a number of pulses of the third control signal in the writing frame is greater than a number of pulses of the first control signal in the writing frame, the data signal comprises at least one pulse in the writing frame; and
a number of pulses of the third control signal in the holding frame is greater than a number of pulses of the first control signal in the holding frame, and a number of pulses of the data signal in the holding frame is zero.

9 . A display panel comprising:
a plurality of pixel circuits according to claim 1 ; and at least two gate driving circuits, one of the gate driving circuits outputting a first driving signal to control the source or the drain of the driving transistor to reset; wherein another of the gate driving circuits outputs a second driving signal to control the anode of the light-emitting device to reset, wherein a frequency of the first driving signal is higher than a frequency of the second driving signal.

10 . The display panel according to claim 9 , wherein the first wiring is a second reset line, and the second wiring is a second control line; one of a source or a drain of the second reset transistor is electrically connected to the source or the drain of the driving transistor, another of the source or the drain of the second reset transistor is electrically connected to the second reset line, and a gate of the second reset transistor is electrically connected to the second control line, and
wherein a number of times the second reset transistor is turned on in the one frame is greater than a number of times the first reset transistor is turned on in the one frame.

11 . The display panel according to claim 10 , wherein the first control line is configured to transmit a first control signal, and the second control line is configured to transmit a second control signal, a number of pulses of the second control signal in the one frame is greater than a number of pulses of the first control sign

Assignees

• Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Chen Tao

Classifications

• G09G2320/0271

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• G09G2320/0247

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• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title