Driving circuitry, driving method, display substrate and display device

Patent metadata

Field	Value
Publication number	US-12592174-B2
Application number	US-202218556639-A
Country	US
Kind code	B2
Filing date	Nov 25, 2022
Priority date	Nov 25, 2022
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

The present disclosure provides a driving circuitry, a driving method, a display substrate and a display device. The driving circuitry includes a driving output circuitry, a first resetting circuitry and a first isolation circuitry. The driving output circuitry is configured to control a driving signal output end to be electrically coupled to a first voltage line or a first clock signal line under the control of a potential at a first node. The first resetting circuitry is configured to control a first clock signal line to write a first clock signal into a first control node under the control of a first resetting signal. The first isolation circuitry is configured to control the first control node to be electrically coupled to the first node under the control of a second clock signal.

First claim

What is claimed is:

1 . A driving circuitry, comprising a driving output circuitry, a first resetting circuitry, a first isolation circuitry, a cascading output circuitry and a cascading resetting circuitry, wherein
the driving output circuitry is electrically coupled to a first node and a driving signal output end, electrically coupled to a first voltage line or a first clock signal line, and configured to control the driving signal output end to be electrically coupled to the first voltage line or the first clock signal line under the control of a potential at the first node; the first resetting circuitry is electrically coupled to a first resetting line, the first clock signal line and a first control node, and configured to control the first clock signal line to write a first clock signal into the first control node under the control of a first resetting signal from the first resetting line; and the first isolation circuitry is electrically coupled to a second clock signal line, the first control node and the first node, and configured to control the first control node to be electrically coupled to the first node under the control of a second clock signal from the second clock signal line; wherein the cascading output circuitry is electrically coupled to the first node, a carry output end and the first voltage line, and configured to control the carry output end to be electrically coupled to the first voltage line under the control of the potential at the first node, and the cascading resetting circuitry is electrically coupled to a second node, the carry output end and a second voltage line, and configured to control the carry output end to be electrically coupled to the second voltage line under the control of a potential at the second node; wherein the cascading resetting circuitry comprises a second transistor and a third transistor; a gate electrode of the second transistor is electrically coupled to the second node, a first electrode of the second transistor is electrically coupled to the carry output end, and a second electrode of the second transistor is electrically coupled to a fourth node; and a gate electrode of the third transistor is electrically coupled to the second node, a first electrode of the third transistor is electrically coupled to the fourth node, and a second electrode of the third transistor is electrically coupled to the second voltage line.

2 . The driving circuitry according to claim 1 , wherein the first resetting circuitry comprises a first transistor, a gate electrode of the first transistor is electrically coupled to the first resetting line, a first electrode of the first transistor is electrically coupled to the first clock signal line, and a second electrode of the first transistor is electrically coupled to the first control node.

3 . The driving circuitry according to claim 2 , wherein the first transistor is an oxide thin film transistor, a first high voltage time period does not overlap with a second high voltage time period, the first high voltage time period is a time period within which a potential of the first clock signal is a high voltage, and the second high voltage time period is a time period within which a potential of the second clock signal is a high voltage.

4 . The driving circuitry according to claim 1 , further comprising a second control node control circuitry coupled to the first clock signal line, the first voltage line, a second control node, a third node and the second clock signal line, and configured to control the second control node to be electrically coupled to the first voltage line under the control of the first clock signal, and control the third node to be electrically coupled to the second clock signal line under the control of a potential at the second control node,
wherein the second control node control circuitry is further configured to control the potential at the second control node in accordance with a potential at the third node.

5 . The driving circuitry according to claim 1 , further comprising a first control circuitry electrically coupled to the first node, a third voltage line and the fourth node, and configured to control the third voltage line to be electrically coupled to the fourth node under the control of the potential at the first node,
wherein the first control circuitry comprises a fourth transistor, a gate electrode of the fourth transistor is electrically coupled to the first node, a first electrode of the fourth transistor is electrically coupled to the third voltage line, and a second electrode of the fourth transistor is electrically coupled to the fourth node.

6 . The driving circuitry according to claim 5 , further comprising a driving output resetting circuitry and a second resetting circuitry, wherein the output resetting circuitry is electrically coupled to the second node, the driving signal output end and a fourth voltage line, and configured to control the driving signal output end to be electrically coupled to the fourth voltage line under the control of the potential at the second node, wherein the second resetting circuitry is electrically coupled to the first node, the second voltage line and the second node, and configured to control the second voltage line to be electrically coupled to the second node under the control of the potential at the first node,
wherein a transistor in the output resetting circuitry is an oxide transistor, and a voltage value of a second voltage signal from the second voltage line is less than a voltage value of a first voltage signal from the first voltage line, wherein the output resetting circuitry comprises a fifth transistor and a first capacitor, and the second resetting circuitry comprises a sixth transistor; a gate electrode of the fifth transistor is electrically coupled to the second node, a first electrode of the fifth transistor is electrically coupled to the driving signal output end, and a second electrode of the fifth transistor is electrically coupled to the fourth voltage line; a first end of the first capacitor is electrically coupled to the second node, and a second end of the first capacitor is electrically coupled to the fourth voltage line; and a gate electrode of the sixth transistor is electrically coupled to the first node, a first electrode of the sixth transistor is electrically coupled to the second voltage line, and a second electrode of the sixth transistor is electrically coupled to the second node.

7 . The driving circuitry according to claim 1 , further comprising a second control circuitry electrically coupled to the first control node, the second clock signal line, the second voltage line and a second control node, and configured to control the first control node to be electrically coupled to the second voltage line under the control of the potential at the second control node and the second clock signal from the second clock signal line,
wherein the driving circuitry further comprises a third control circuitry electrically coupled to the second clock signal line, an input line and the first control node, and configured to control the input line to be electrically coupled to the first control node under the control of the second clock signal, wherein the driving circuitry further comprises a fourth control circuitry electrically coupled to the first node, the first control node and the third voltage line, and configured to control the first control node to be electrically coupled to the third voltage line under the control of the potential at the first node.

8 . The driving circuitry according to claim 6 , wherein the second control node control circuitry is further electrically coupled to the input line, and configured to write the first clock signal into the sec

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhao Donghui
• Xu Pan
• Han Ying
• Zhang Xing
• Luo Chengyuan
• Lv Guangshuang
• Yao Xing
• Zhou Dandan
• Liu Miao

Classifications

• G09G2320/0214

  with crosstalk due to leakage current of pixel switch in active matrix panels · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title