System and method for securing high-speed intrachip communications

Patent metadata

Field	Value
Publication number	US-12591545-B2
Application number	US-202418904106-A
Country	US
Kind code	B2
Filing date	Oct 2, 2024
Priority date	Oct 30, 2017
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A system and method for securing high-speed communications between processing units on computer chips, wherein a training data set is used to find patterns and associated smaller indices, or codewords, which are stored in a reference codebook library, and where reconstruction and deconstruction algorithms are used to encode and decode data as it is received. The codebook and algorithms may be stored in the firmware of a semiconductor which enable reduced resources and cost when transmitting data between or among devices that utilize such semiconductors.

First claim

What is claimed is:

1 . A system for securing high-speed intrachip communications, comprising:
a complex chip comprising at least two processors and a memory for each processor; wherein each processor stores a reference data structure in its respective memory, wherein:
the reference data-structure is generated by using training data to identify input patterns and their associated compressed representations;
compressed representations within the reference data structure are assigned such that input patterns that occur more frequently are assigned shorter compressed representations based on a combination of:
an observed frequency of occurrence of input patterns in the training data; and
an estimated frequency of occurrence of input patterns not in the training data;

the assignment of shorter compressed representations to more frequently-occurring input patterns is dynamically updated based on ongoing analysis of data transmitted between the processors, combining both the observed frequency in the training data and the estimated frequency of input patterns not in the training data, thereby adapting the reference data structure to evolving communication patterns between the processors.

2 . The system of claim 1 , further comprising:
wherein each of a first processor and a second processor on the complex chip stores a deconstruction algorithm in respective memory, wherein the deconstruction algorithm, when operating on the first processor, causes the first processor to:
receive data;
deconstruct the data into a plurality of input patterns; and
encode the data by retrieving the compressed representation for each input pattern from the reference data structure.

3 . The system of claim 1 , further comprising:
wherein each of a first processor and a second processor on the complex chip stores a reconstruction algorithm embedded as firmware in its respective memory, wherein the reconstruction algorithm, when operating on the second processor, causes the second processor to:
receive a compressed representation;
retrieve an input pattern for each received compressed representation from the reference data structure; and
assemble the input pattern to reconstruct the data.

4 . A method for securing high-speed intrachip communications, comprising:
a complex chip comprising at least two processors and a memory for each processor; wherein each processor stores a reference data structure in its respective memory, wherein:
the reference data-structure is generated by using training data to identify input patterns and their associated compressed representations;
compressed representations within the reference data structure are assigned such that more frequently-occurring input patterns are assigned shorter compressed representations based on a combination of:
an observed frequency of occurrence of input patterns in the training data; and
an estimated frequency of occurrence of input patterns not in the training data;

the assignment of shorter compressed representations to more frequently-occurring input patterns is dynamically updated based on ongoing analysis of data transmitted between the processors, combining both the observed frequency in the training data and the estimated frequency of input patterns not in the training data, thereby adapting the reference data structure to evolving communication patterns between the processors.

5 . The method of claim 4 , further comprising the steps of:
storing a deconstruction algorithm embedded as firmware in the memory of the first processor-and in the memory of the second processor, wherein the deconstruction algorithm, when operating on the first processor, causes the first processor to:
receive data;
deconstruct the data into a plurality of input patterns; and
encode the data by retrieving the compressed representation for each input pattern from the reference data structure.

6 . The method of claim 4 , further comprising the steps of:
storing a reconstruction algorithm embedded as firmware in the memory of the first processor and in the memory of the second processor, wherein the reconstruction algorithm, when operating on the second processor, causes the second processor to:
receive a compressed representation;
retrieve an input pattern for each received compressed representation from the reference data structure; and
assemble the input pattern to reconstruct the data.

Assignees

• Atombeam Technologies Inc
• Atom Beam Tech Inc

Inventors

• Cooper Joshua
• Yeomans Charles
• Riahi Aliasghar
• Caltabiano Gregory
• Haddad Mojgan

Classifications

• G06F3/0608

  Saving storage space on storage systems · CPC title

• G06F3/0641

  De-duplication techniques · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

• H03M7/6047

  Power optimization with respect to the encoder, decoder, storage or transmission · CPC title

• H03M7/405

  Tree adaptation · CPC title