Configurable stream switch with virtual channels for the sharing of I/O ports in stream-based architectures

Patent metadata

Field	Value
Publication number	US-12591533-B2
Application number	US-202318304938-A
Country	US
Kind code	B2
Filing date	Apr 21, 2023
Priority date	Apr 21, 2023
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A stream switch includes a data router, configuration registers, and arbitration logic. The data router has a plurality of input ports, each having a plurality of associated virtual input channels, and a plurality of output ports, each having a plurality of associated virtual output channels. The data router transmits data streams from input ports to one or more output ports of the plurality of output ports. The configuration registers store configuration data associated with the virtual output channels of the respective output ports of the plurality of output ports. The stored configuration data identifies a source input port and virtual input channel ID associated with the virtual output channel of the output port. The arbitration logic allocates bandwidth of the data router based on request signals associated with virtual input channels of the input ports and the configuration data associated with the virtual output channels.

First claim

The invention claimed is:

1 . A stream switch, comprising:
a data router having: a plurality of input ports, each input port having plurality of associated virtual input channels; and a plurality of output ports, each output port having a plurality of associated virtual output channels, wherein the data router, in operation, streams data tensors from input ports of the plurality of input ports to one or more output ports of the plurality of output ports; configuration registers coupled to the data router, wherein the configuration registers, in operation, store configuration data associated with the virtual output channels of the respective output ports of the plurality of output ports, the stored configuration data associated with a virtual output channel identifying a source input port and virtual input channel ID associated with the virtual output channel of the output port; and arbitration logic that performs output-level arbitration using a plurality of arbitrators corresponding to respective output ports of the plurality of output ports and comprises a master arbitrator that resolves conflicts between the plurality of arbitrators, wherein the arbitration logic is coupled to the configuration registers and the data router, wherein the arbitration logic, in operation, allocates bandwidth of the data router based on request signals associated with virtual input channels of the input ports and the configuration data associated with the virtual output channels.

2 . The stream switch of claim 1 , wherein the arbitration logic, in operation, generates stall signals associated with respective virtual input channels, and a stall signal inhibits transmission of data by a source associated with the respective virtual input channel and the stall signal.

3 . The stream switch of claim 2 , comprising a stall router, which, in operation, routes stall signals to respective sources associated with virtual input channels of the input ports.

4 . The stream switch of claim 1 , wherein the arbitration logic, in operation, employs a round-robin prioritization scheme to allocate the bandwidth.

5 . The stream switch of claim 1 , wherein the arbitration logic, in operation, implements a back-pressure mechanism based on an indication of whether a destination IP associated with an output port is ready to receive data.

6 . The stream switch of claim 1 , comprising a request router, which, in operation, routes request signals associated with virtual input channels to the arbitration logic based on the stored configuration data.

7 . The stream switch of claim 1 , comprising destination routing circuitry, which, in operation, streams a data tensor received at an input port to an output port of the data router based on a virtual input channel ID associated with the received data tensor and the stored configuration data.

8 . The stream switch of claim 1 , wherein the data router comprises:
an additional input port having an associated virtual input channel; an additional output port having an associated virtual output channel; or an additional input port having an associated virtual input channel and an additional output port having an associated virtual output channel.

9 . The stream switch of claim 1 , wherein a request signal associated with an input port of the plurality of input ports is a bitmap, with each bit of the bitmap indicating whether a source associated with a respective virtual input channel associated with the input port is requesting bandwidth to transmit a data tensor via the input port.

10 . The stream switch of claim 3 , wherein a stall signal associated with an input port of the plurality of input ports is a bitmap, with each bit of the bitmap indicating whether a source associated with a respective virtual input channel associated with the input port is allowed to transmit a data tensor via the input port.

11 . A hardware accelerator, comprising:
a plurality of processing elements; a plurality of streaming engines; and a stream switch coupled to the plurality of processing elements and to the plurality of streaming engines, wherein the stream switch, in operation, streams data tensors between the plurality of streaming engines and the plurality of processing elements, the stream switch including: a data router having: a plurality of input ports, each input port having a plurality of associated virtual input channels; and a plurality of output ports, each output port having a plurality of associated virtual output channels, wherein the data router, in operation, transmits data tensors from input ports of the plurality of input ports to one or more output ports of the plurality of output ports; configuration registers coupled to the data router, wherein the configuration registers, in operation, store configuration data associated with the virtual output channels of the respective output ports of the plurality of output ports, the stored configuration data associated with a virtual output channel identifying a source input port and virtual input channel ID associated with the virtual output channel of the output port; and arbitration logic that performs output-level arbitration using a plurality of arbitrators corresponding to respective output ports of the plurality of output ports and comprises a master arbitrator that resolves conflicts between the plurality of arbitrators, wherein the arbitration logic is coupled to the configuration registers and the data router, wherein the arbitration logic, in operation, allocates bandwidth of the data router based on request signals associated with virtual input channels of the input ports and the configuration data associated with the virtual output channels.

12 . The hardware accelerator of claim 11 , wherein the arbitration logic, in operation, generates stall signals associated with respective virtual input channels, and a stall signal inhibits transmission of data by a source associated with the respective virtual input channel and the stall signal.

13 . The hardware accelerator of claim 11 , wherein the arbitration logic, in operation, implements a back-pressure mechanism based on an indication of whether a destination IP associated with an output port is ready to receive data.

14 . The hardware accelerator of claim 13 , wherein the destination associated with the output port is a processing element of the plurality of processing elements.

15 . The hardware accelerator of claim 11 , wherein the plurality of virtual input channels associated with an input port of the plurality of input ports includes:
a virtual input channel associated with a processing element of the plurality of processing elements; and a virtual input channel associated with a streaming engine of the plurality of streaming engines.

16 . The hardware accelerator of claim 11 , wherein a request signal associated with an input port of the plurality of input ports is a bitmap, with each bit of the bitmap indicating whether a source associated with a respective virtual input channel associated with the input port is requesting bandwidth to transmit a data tensor via the input port.

17 . The hardware accelerator of claim 12 , wherein a stall signal associated with an input port of the plurality of input ports is a bitmap, with each bit of the bitmap indicating whether a source associated with a respective virtual input channel associated with the input port is allowed to transmit a data tensor via the input port.

18 . The hardware accelerator of claim 11 , wherein the arbitration logic, in operation, emplo

Assignees

• St Microelectronics Int Nv

Inventors

• De Vita Antonio
• Boesch Thomas
• Desoli Giuseppe

Classifications

• G06F2209/5011

  Pool · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• H04L49/506

  Backpressure · CPC title

• H04L49/3045

  Virtual queuing · CPC title

• G06N3/063

  using electronic means · CPC title