Memory system and method

Patent metadata

Field	Value
Publication number	US-12591393-B2
Application number	US-202318535956-A
Country	US
Kind code	B2
Filing date	Dec 11, 2023
Priority date	Jan 20, 2023
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller. The controller is electrically connected to the nonvolatile memory. The controller determines lanes to be set to an operating state among a plurality of lanes of a link between the host and the memory system, based on first information on one or more commands issued by the host. The controller sets the determined lanes among the plurality of lanes to the operating state. The controller sets lanes other than the determined lanes among the plurality of lanes to a low power consumption state.

First claim

What is claimed is:

1 . A memory system connectable to a host, comprising:
a random access memory; a nonvolatile memory; and a controller electrically connected to the nonvolatile memory and configured to:
determine lanes to be set to an operating state among a plurality of lanes of a link between the host and the memory system, based on first information on one or more commands issued by the host, the first information including storage completion information indicating that data to be written into the nonvolatile memory in accordance with at least one of the one or more commands has been stored in the random access memory;
decrease the number of the lanes set to the operating state in accordance with the storage completion information;
set the determined lanes among the plurality of lanes to the operating state; and
set lanes other than the determined lanes among the plurality of lanes to a low power consumption state.

2 . The memory system of claim 1 , wherein
the first information further includes information on a first number of commands that have been issued by the host but for which corresponding processes have not yet been performed in the memory system, and the controller is further configured to:
as the first number of commands increase, increase the number of the lanes set to the operating state; and
as the first number of commands decrease, decrease the number of the lanes set to the operating state.

3 . The memory system of claim 1 , wherein
the first information further includes information on a second number of commands that have been issued by the host but have not yet been accepted by the memory system, and the controller is further configured to:
as the second number of commands increase, increase the number of the lanes set to the operating state; and
as the second number of commands decrease, decrease the number of the lanes set to the operating state.

4 . The memory system of claim 1 , wherein
the first information further includes information on a third number of commands that have been issued by the host and accepted by the memory system, but for which corresponding processes have not yet been executed in the memory system, and the controller is further configured to:
as the third number of commands increase, increase the number of the lanes set to the operating state; and
as the third number of commands decrease, decrease the number of the lanes set to the operating state.

5 . The memory system of claim 1 , wherein
the first information further includes information on a fourth number of commands that have been issued by the host and accepted by the memory system, and for which corresponding processes have been partially executed in the memory system but for which all the processes have not yet been completed, and the controller is further configured to:
as the fourth number of commands increase, increase the number of the lanes set to the operating state; and
as the fourth number of commands decrease, decrease the number of the lanes set to the operating state.

6 . The memory system of claim 1 , wherein
the first information further includes information indicative of a first data amount and information indicative of a second data amount, the first data amount being an amount of data that has not yet been transferred among data to be transferred from the host to the memory system in accordance with at least one of the one or more commands, the second data amount being an amount of data that has not yet been transferred among data to be transferred from the memory system to the host in accordance with at least one of the one or more commands, and the controller is further configured to:
as a sum of the first data amount and the second data amount increases, increase the number of the lanes set to the operating state; and
as the sum decreases, decrease the number of the lanes set to the operating state.

7 . The memory system according to claim 1 , wherein
the controller is configured to determine the lanes to be set to the operating state while the link is in a link power state L0p specified in a PCIe standard.

8 . A memory system connectable to a host, comprising:
a random access memory; a nonvolatile memory; and a controller electrically connected to the nonvolatile memory and configured to:
determine lanes to be set to an operating state among a plurality of lanes of a link between the host and the memory system, based on first information on one or more commands issued by the host, the first information including storage completion information indicating that data read from the nonvolatile memory in accordance with at least one of the one or more commands has been stored in the random access memory;
increase the number of the lanes set to the operating state in accordance with the storage completion information;
set the determined lanes among the plurality of lanes to the operating state; and
set lanes other than the determined lanes among the plurality of lanes to a low power consumption state.

9 . The memory system of claim 8 , wherein
the first information further includes information on a first number of commands that have been issued by the host but for which corresponding processes have not yet been performed in the memory system, and the controller is further configured to:
as the first number of commands increase, increase the number of the lanes set to the operating state; and
as the first number of commands decrease, decrease the number of the lanes set to the operating state.

10 . The memory system of claim 8 , wherein
the first information further includes information on a second number of commands that have been issued by the host but have not yet been accepted by the memory system, and the controller is further configured to:
as the second number of commands increase, increase the number of the lanes set to the operating state; and
as the second number of commands decrease, decrease the number of the lanes set to the operating state.

11 . The memory system of claim 8 , wherein
the first information further includes information on a third number of commands that have been issued by the host and accepted by the memory system, but for which corresponding processes have not yet been executed in the memory system, and the controller is further configured to:
as the third number of commands increase, increase the number of the lanes set to the operating state; and
as the third number of commands decrease, decrease the number of the lanes set to the operating state.

12 . The memory system of claim 8 , wherein
the first information further includes information on a fourth number of commands that have been issued by the host and accepted by the memory system, and for which corresponding processes have been partially executed in the memory system but for which all the processes have not yet been completed, and the controller is further configured to:
as the fourth number of commands increase, increase the number of the lanes set to the operating state; and
as the fourth number of commands decrease, decrease the number of the lanes set to the operating state.

13 . The memory system of claim 8 , wherein
the first information further includes information indicative of a first data amount and information indicative of a second data amount, the first data amount being an amount of data that has not yet been transferred among data to be transferred from the host to the memory system in accordance with at least one of the one or more commands, the second data amount being an amount of data that has not yet been transf

Assignees

• Kioxia Corp

Inventors

• Ishiguro Takashi

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F1/32

  Means for saving power · CPC title