Method for fabricating multiple work function layers

Patent metadata

Field	Value
Publication number	US-12588442-B2
Application number	US-202318355369-A
Country	US
Kind code	B2
Filing date	Jul 19, 2023
Priority date	Nov 22, 2022
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

The present application provides a method for fabricating multiple work function layers, including: forming the first to the nth transistor gates with notches; forming a blocking layer in the notches; depositing the first work function layer and removing the first work function layer on the first to the (n−1)th transistor gates; depositing a second work function layer; removing the second work function layer on the first to the (n−2)th transistor gates; depositing a third work function layer on the blocking layer on the first to the (n−2)th transistor gates and the second work function layer on the (n−1)th and nth transistor gates; removing the third work function layer on the first to (n−3)th transistor gates; depositing the third to the (n−1)th work function layers by analogy until only the blocking layer exists on the last transistor gate, herein the thickness of the third to the (n−1)th work function layers decreases sequentially and gradually.

First claim

What is claimed is:

1 . A method for fabricating multiple work function layers, at least comprising:
step 1: providing a substrate, forming n transistor gates from a first to an nth transistor gates on the substrate, wherein each of the n transistor gates comprises a different work function from each other, where n is a natural number greater than or equal to 3; forming notches in the first to the nth transistor gates; and forming an HK layer and a blocking layer sequentially on the HK layer in the notches; step 2: depositing a first work function layer on the blocking layer on the first to the nth transistor gates, removing the first work function layer from above the first to the (n−1)th transistor gates through a first process of photolithography and etching, wherein the first process reserves the first work function layer above the nth transistor gate; step 3: depositing a second work function layer on the blocking layer and on the first to the (n−1)th transistor gates and the first work function layer above the nth transistor gate, removing the second work function layer from above the first to the (n−2)th transistor gates through a second process of photolithography and etching, wherein the second process reserves the second work function layer above the (n−1)th and nth transistor gates, wherein a thickness of the second work function layer is less than a thickness of the first work function layer; step 4: depositing a third work function layer on the blocking layer, the first to the (n−2)th transistor gates and the second work function layer above the (n−1)th and the nth transistor gates, removing the third work function layer from above the first to (n−3)th transistor gates through a third process of photolithography and etching, wherein the third process reserves the third work function layer above the (n−2)th, (n−1)th and nth transistor gates, wherein a thickness of the third work function layer is less than the thickness of the second work function layer; step 5: in a case that there are more than 4 transistor gates, wherein each of which has a different work function from each other, depositing a third to (n−1)th work function layers sequentially by analogy according to step 2 to step 4 until only the blocking layer exists on a last transistor gate, wherein thicknesses of the deposited third to the (n−1)th work function layers decrease sequentially and gradually; and step 6: sequentially forming a TiAlC layer, a TiN layer, and a back-end metal connecting hole from bottom to top.

2 . The method for fabricating the multiple work function layers according to claim 1 , wherein in step 1, the n transistors having different work functions comprise pFET and nFET.

3 . The method for fabricating the multiple work function layers according to claim 1 , wherein in step 1, the blocking layer comprises a TiNO layer and a TaN layer disposed on the TiNO layer.

4 . The method for fabricating the multiple work function layers according to claim 1 , wherein in step 2, removing the first work function layer from above the first to the (n−1)th transistor gates through a fourth process of photolithography and etching, and reserving the first work function layer above the nth transistor gate comprises: spin-coating a photoresist on the first work function layer, exposing and developing the first work function layer above the first to the (n−1)th transistor gates with a first mask, and finally removing the exposed first work function layer through etching, wherein the first work function layer above the nth transistor gate is not etched under protection of the first mask layer on the photoresist.

5 . The method for fabricating the multiple work function layers according to claim 1 , wherein in step 2, depositing the first work function layer is via atomic layer deposition.

6 . The method for fabricating the multiple work function layers according to claim 1 , wherein in step 3, depositing the second work function layer is via atomic layer deposition.

7 . The method for fabricating the multiple work function layers according to claim 1 , wherein in step 1, the n transistors with different work functions comprise from a first transistor gate to a fourth transistor gate, wherein notches are formed in all of the four transistor gates, and wherein an high dielectric constant (HK) layer and a blocking layer disposed on the HK layer are sequentially formed in the notches.

8 . The method for fabricating the multiple work function layers according to claim 7 , wherein step 2 further comprises depositing a first work function layer on the blocking layer and the first to fourth transistor gates, and removing the first work function layer from above the first to third transistor gates through a fifth process of photolithography and etching, wherein the fifth process reserves the first work function layer above the fourth transistor gate.

9 . The method for fabricating the multiple work function layers according to claim 8 , wherein step 3 further comprises depositing a second work function layer on the blocking layer, the first to third transistor gates, and the first work function layer above the fourth transistor gate, and removing the second work function layer above the first and second transistor gates through a sixth process of photolithography and etching, and wherein the sixth process reserves the second work function layer above the third and fourth transistor gates, wherein a thickness of the second work function layer is less than the thickness of the first work function layer.

10 . The method for fabricating the multiple work function layers according to claim 9 , wherein step 4 further comprises depositing a third work function layer on the blocking layer, the first and second transistor gates, and the second work function layer above the third and fourth transistor gates, and removing the third work function layer from above the first transistor gate through a seventh process of photolithography and etching, wherein the seventh process reserves the third work function layer above the second, third and fourth transistor gates, wherein a thickness of the third work function layer is less than the thickness of the second work function layer.

11 . The method for fabricating the multiple work function layers according to claim 7 , wherein in step 2, the first work function layer comprises a TiN layer, and wherein the thickness of the first work function layer is about 23 angstroms.

12 . The method for fabricating the multiple work function layers according to claim 7 , wherein in step 3, the second work function layer comprises a TiN layer, and wherein the thickness of the second work function layer is about 13 angstroms.

13 . The method for fabricating the multiple work function layers according to claim 7 , wherein in step 4, the third work function layer comprises a TiN layer, and wherein the thickness of the third work function layer is about 10 angstroms.

Assignees

• Shanghai Huali Integrated Circuit Corp

Inventors

• Zheng Hongzhu
• Wang Jian
• Dai Yunqing
• Zhou Wenzhan

Classifications

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/853

  comprising FinFETs · CPC title