Semiconductor structure with memory device and method for manufacturing the same
US-2022302375-A1 · Sep 22, 2022 · US
Semiconductor device and method for fabricating the same
US12588422B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12588422-B2 |
| Application number | US-202217972569-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 24, 2022 |
| Priority date | Sep 26, 2022 |
| Publication date | Mar 24, 2026 |
| Grant date | Mar 24, 2026 |
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Abstract
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A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a metal interconnection in the IMD layer, forming a magnetic tunneling junction (MTJ) on the metal interconnection, and performing a trimming process to shape the MTJ. Preferably, the MTJ includes a first slope and a second slope and the first slope is less than the second slope.
First claim
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What is claimed is: 1 . A semiconductor device, comprising: an inter-metal dielectric (IMD) layer on a substrate; a metal interconnection in the IMD layer; a bottom electrode on the metal interconnection; a magnetic tunneling junction (MTJ) on the bottom electrode, wherein a sidewall of the MTJ comprises a first slope and a second slope, the first slope is less than the second slope, and the MTJ comprises: a pinned layer on the bottom electrode, wherein the bottom electrode and the pinned layer comprise the first slope. 2 . The semiconductor device of claim 1 , further comprising: the MTJ on the bottom electrode, wherein the MTJ comprises: the pinned layer on the bottom electrode; a barrier layer on the pinned layer; a free layer on the barrier layer; a top electrode on the MTJ; and a hard mask on the top electrode. 3 . The semiconductor device of claim 2 , wherein the pinned layer comprises the first slope. 4 . The semiconductor device of claim 2 , wherein the free layer comprises the second slope. 5 . The semiconductor device of claim 2 , wherein the top electrode comprises the second slope. 6 . The semiconductor device of claim 2 , wherein the hard mask and the top electrode comprise different slopes.
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Frequently asked questions
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- What does patent US12588422B2 cover?
- A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a metal interconnection in the IMD layer, forming a magnetic tunneling junction (MTJ) on the metal interconnection, and performing a trimming process to shape the MTJ. Preferably, the MTJ includes a first slope and a second slope and the first slope is less t…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10N50/01. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 24 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).