Display apparatus including a thin-film transistor including a silicon semiconductor and a thin-film transistor including an oxide semiconductor
US-11574972-B2 · Feb 7, 2023 · US
US12588370B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12588370-B2 |
| Application number | US-202318129781-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 31, 2023 |
| Priority date | Jun 30, 2022 |
| Publication date | Mar 24, 2026 |
| Grant date | Mar 24, 2026 |
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Provided is a display apparatus including: a substrate having a display area, a first corner area, and a second corner area disposed outside the first corner area; an inorganic insulating layer disposed on the substrate; a first planarization layer and a second planarization layer disposed on the inorganic insulating layer, each of the first planarization layer and the second planarization layer overlapping the first corner area; a third planarization layer disposed on the second planarization layer and overlapping the first corner area and the second corner area; a display element layer disposed on the third planarization layer; a first shielding layer disposed on the third planarization layer and overlapping the first corner area and the second corner area, wherein a plurality of first holes are defined in the first shielding layer; and a second shielding layer disposed on the inorganic insulating layer and overlapping the second corner area.
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What is claimed is: 1 . A display apparatus comprising: a substrate including a display area, a first corner area disposed at a corner of the display area, and a second corner area disposed outside the first corner area; an inorganic insulating layer disposed on the substrate; a first planarization layer and a second planarization layer disposed on the inorganic insulating layer, each of the first planarization layer and the second planarization layer overlapping the first corner area; a third planarization layer disposed on the second planarization layer and overlapping the first corner area and the second corner area; a display element layer disposed on the third planarization layer, the display element layer including a pixel electrode, an emission layer, and an opposite electrode; a first shielding layer disposed on the third planarization layer and overlapping the first corner area and the second corner area, wherein a plurality of first holes are defined in the first shielding layer; and a second shielding layer disposed on the inorganic insulating layer and overlapping the second corner area, wherein the second shielding layer is in direct contact with the inorganic insulating layer in the second corner area. 2 . The display apparatus of claim 1 , wherein the opposite electrode extends from the display area to the first corner area, and the first corner area is covered with the first shielding layer and the opposite electrode in a plan view. 3 . The display apparatus of claim 1 , further comprising a third shielding layer disposed between the second planarization layer and the third planarization layer and overlapping the first corner area, wherein a plurality of second holes are defined in the third shielding layer, wherein the plurality of first holes overlap the plurality of second holes. 4 . The display apparatus of claim 3 , wherein an overlapping area of the plurality of first holes and the plurality of second holes is 13% or more of a total area of the first corner area. 5 . The display apparatus of claim 3 , wherein the second shielding layer and the third shielding layer are integrally formed as a single body. 6 . The display apparatus of claim 1 , wherein the second corner area is covered with the first shielding layer and the second shielding layer in a plan view. 7 . A display apparatus comprising: a substrate comprising a display area, a first peripheral area surrounding at least a portion of the display area, and a second peripheral area disposed outside the first peripheral area; an inorganic insulating layer disposed on the substrate; a first planarization layer, a second planarization layer, and a third planarization layer sequentially disposed on the inorganic insulating layer in this stated order; a display element layer disposed on the third planarization layer, the display element layer including a pixel electrode, an emission layer, and an opposite electrode; a first shielding layer disposed on the third planarization layer, wherein a plurality of first holes are defined in the first shielding layer; a second shielding layer disposed on the second planarization layer and overlapping the first peripheral area, wherein a plurality of second holes are defined in the second shielding layer; and a third shielding layer disposed between the inorganic insulating layer and the second planarization layer and overlapping the second peripheral area, wherein a plurality of third holes are defined in the third shielding layer. 8 . The display apparatus of claim 7 , wherein the opposite electrode extends from the display area to the first peripheral area, and the first peripheral area is covered with the first shielding layer, the second shielding layer, and the opposite electrode in a plan view. 9 . The display apparatus of claim 7 , further comprising a valley portion passing through the first planarization layer, the second planarization layer, and the third planarization layer, wherein the first shielding layer covers the valley portion. 10 . The display apparatus of claim 9 , wherein the plurality of first holes are spaced apart from the valley portion. 11 . The display apparatus of claim 7 , further comprising a valley portion passing through the first planarization layer, the second planarization layer, and the third planarization layer, wherein the opposite electrode covers the valley portion. 12 . The display apparatus of claim 7 , further comprising: a first driving circuit disposed between the substrate and the first planarization layer and overlapping the first peripheral area; and a second driving circuit disposed between the substrate and the first planarization layer and overlapping the second peripheral area. 13 . The display apparatus of claim 7 , wherein an overlapping area of the plurality of first holes and the plurality of second holes in the first peripheral area is 13% or more of a total area of the first peripheral area. 14 . The display apparatus of claim 7 , wherein the second peripheral area is covered with the first shielding layer and the third shielding layer in a plan view. 15 . The display apparatus of claim 7 , further comprising a fourth shielding layer overlapping the second peripheral area, wherein a plurality of fourth holes are defined in the fourth shielding layer, wherein the fourth shielding layer is disposed on a layer that is different from the third shielding layer, and the second peripheral area is covered with the first shielding layer, the third shielding layer, and the fourth shielding layer in a plan view. 16 . The display apparatus of claim 7 , further comprising: a fourth shielding layer disposed on the second planarization layer and overlapping the second peripheral area, wherein a plurality of fourth holes are defined in the fourth shielding layer; and a fifth shielding layer disposed on the inorganic insulating layer and overlapping the second peripheral area, wherein a plurality of fifth holes are defined in the fifth shielding layer, wherein the second peripheral area is covered with the first shielding layer, the third shielding layer, the fourth shielding layer, and the fifth shielding layer in a plan view. 17 . A display apparatus comprising: a substrate comprising a display area, a first peripheral area surrounding at least a portion of the display area, and a second peripheral area disposed outside the first peripheral area; an inorganic insulating layer disposed on the substrate; a first planarization layer, a second planarization layer, and a third planarization layer sequentially disposed on the inorganic insulating layer in this stated order; a display element layer disposed on the third planarization layer, the display element layer comprising a pixel electrode, an emission layer, and an opposite electrode; a first shielding layer disposed on the third planarization layer, wherein a plurality of first holes are defined in the first shielding layer; a third shielding layer between the inorganic insulating layer and the second planarization layer and overlapping the second peripheral area, wherein a plurality of third holes are defined in the third shielding layer; and a fourth shielding layer disposed on a layer that is different from the first shielding layer and the third shielding layer and overlapping the second peripheral area, wherein a plurality of fourth holes are defined in the fourth shielding layer. 18 . The display apparatus of claim 17 , wherein the opposite electrode extends from the
Shielding, e.g. light-blocking means over the TFTs · CPC title
characterised by their shape · CPC title
Encapsulations · CPC title
Interconnections, e.g. wiring lines or terminals · CPC title
Insulating layers formed between TFT elements and OLED elements · CPC title
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