Display device

Patent metadata

Field	Value
Publication number	US-12588336-B2
Application number	US-202217945437-A
Country	US
Kind code	B2
Filing date	Sep 15, 2022
Priority date	Dec 15, 2021
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A display device includes a first lower conductive pattern, a second lower conductive pattern, a third lower conductive pattern, a first high power line, a second high power line, and an initialization line, which are disposed in a same layer as each other. The first high power line is disposed between the first lower conductive pattern and the second lower conductive pattern, the second high power line is disposed between the second lower conductive pattern and the third lower conductive pattern, and the initialization line is disposed between the second lower conductive pattern and the third lower conductive pattern.

First claim

What is claimed is:

1 . A display device comprising:
a first lower conductive pattern disposed on a substrate; a second lower conductive pattern disposed in a same layer as the first lower conductive pattern and spaced apart from the first lower conductive pattern; a third lower conductive pattern disposed in a same layer as the second lower conductive pattern and spaced apart from the second lower conductive pattern; a first high power line disposed in a same layer as the third lower conductive pattern and disposed between the first lower conductive pattern and the second lower conductive pattern; a second high power line disposed in a same layer as the first high power line and disposed between the second lower conductive pattern and the third lower conductive pattern; and an initialization line disposed in a same layer as the second high power line and disposed between the second lower conductive pattern and the third lower conductive pattern, wherein the first lower conductive pattern, the second lower conductive pattern, the third lower conductive pattern, the first high power line, the second high power line, and the initialization line are included in a first conductive layer, and wherein the display device further comprises an active layer disposed on the first conductive layer.

2 . The display device of claim 1 , further comprising:
a first data line disposed in a same layer as the initialization line and adjacent to the first lower conductive pattern; a second data line disposed in a same layer as the first data line and disposed between the second lower conductive pattern and the third lower conductive pattern; and a third data line disposed in a same layer as the second data line and adjacent to the third lower conductive pattern.

3 . The display device of claim 2 , wherein the active layer comprises:
a first active pattern disposed on the first lower conductive pattern, overlapping the first lower conductive pattern, and electrically connected to the first data line.

4 . The display device of claim 3 , further comprising:
a first gate line disposed on the first active pattern and partially overlapping the first active pattern.

5 . The display device of claim 4 , wherein a first data voltage applied to the first data line is transferred to the first active pattern in response to a first gate signal applied to the first gate line.

6 . The display device of claim 4 , further comprising:
a first data connection pattern disposed in a same layer as the first gate line and connecting the first data line and the first active pattern to each other.

7 . The display device of claim 3 , wherein the active layer comprises:
a second active pattern disposed on the first lower conductive pattern and electrically connected to the initialization line.

8 . The display device of claim 7 , further comprising:
a first gate pattern disposed on the second active pattern and overlapping the second active pattern.

9 . The display device of claim 8 , wherein an initialization voltage applied to the initialization line is transferred to the second active pattern in response to a second gate signal applied to the first gate pattern.

10 . The display device of claim 8 , further comprising:
an initialization connection pattern disposed on the initialization line and connecting the initialization line and the second active pattern to each other.

11 . The display device of claim 10 , further comprising:
a first data line disposed in a same layer as the initialization line, adjacent to the first lower conductive pattern, and not overlapping the initialization connection pattern.

12 . The display device of claim 1 , wherein the first high power line is electrically connected to the first lower conductive pattern and the second lower conductive pattern.

13 . The display device of claim 1 , wherein the active layer comprises:
a first active pattern disposed on the first lower conductive pattern, overlapping the first lower conductive pattern, and electrically connected to a first data line; a second active pattern disposed in a same layer as the first active pattern and electrically connected to the initialization line; and a third active pattern disposed on the second lower conductive pattern, overlapping the second lower conductive pattern, and electrically connected to a second data line, and wherein the display device further comprises a first pixel electrode disposed on the first active pattern, electrically connected to the first lower conductive pattern, and not overlapping the third active pattern.

14 . The display device of claim 13 , further comprising:
a second pixel electrode disposed on the third active pattern, electrically connected to the second lower conductive pattern, and not overlapping the first active pattern.

15 . The display device of claim 14 , further comprising:
a third pixel electrode disposed on the third lower conductive pattern, electrically connected to the third lower conductive pattern, and not overlapping the first active pattern and the third active pattern, and wherein the first pixel electrode, the second pixel electrode, and the third pixel electrode are arranged in a triangular shape in a plan view.

16 . A display device comprising:
a lower conductive pattern disposed on a substrate and extending in a first direction; a first high power line disposed in a same layer as the lower conductive pattern, extending in the first direction, and adjacent to the lower conductive pattern in a second direction crossing the first direction; a second high power line disposed in a same layer as the first high power line, extending in the first direction, and adjacent to the lower conductive pattern in a third direction opposite to the second direction; and an initialization line disposed in a same layer as the second high power line, extending in the first direction, and adjacent to the lower conductive pattern in the third direction, wherein the lower conductive pattern, the first high power line, the second high power line, and the initialization line are included in a first conductive layer, and wherein the display device further comprises an active layer disposed on the first conductive layer.

17 . The display device of claim 16 , wherein the initialization line is disposed between the lower conductive pattern and the second high power line.

18 . The display device of claim 16 , further comprising:
a data line disposed in a same layer as the initialization line and adjacent to the lower conductive pattern in the third direction.

19 . The display device of claim 18 , wherein the active layer comprises:
a first active pattern disposed on the lower conductive pattern, overlapping the lower conductive pattern, and electrically connected to the data line.

20 . The display device of claim 19 , wherein the active layer comprises:
a second active pattern disposed on the lower conductive pattern and electrically connected to the initialization line.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Sunkwang
• Moon Sungjae
• Lee Seongyoung
• Cheon Soohong

Classifications

• H10H20/8312

  extending at least partially through the bodies · CPC title

• H10K59/123

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title

• H10K59/121

  characterised by the geometry or disposition of pixel elements · CPC title

• H10W90/00

  Package configurations · CPC title

• H10D30/6723

  having light shields · CPC title