Electrostatic discharge protection circuit using GaN-based devices

Patent metadata

Field	Value
Publication number	US-12588293-B2
Application number	US-202418657821-A
Country	US
Kind code	B2
Filing date	May 8, 2024
Priority date	Apr 12, 2024
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

An ESD protection circuit using GaN devices, with an ESD protection block including a first sub-block and a second sub-block. The first sub-block includes a trigger coupled to a gate of a power HEMT, a 2DEG resistor coupled to another terminal of the trigger, a LV-HEMT with a gate coupled to another terminal of the trigger and one terminal of the 2DEG resistor and with a source coupled to the gate of the power HEMT and the terminal of the trigger, and a lateral FER coupled to the gate of the LV-HEMT, the another terminal of the trigger and one terminal of the 2DEG resistor, wherein the second sub-block is provided with a device configuration completely symmetrical to the first sub-block, and corresponding devices of the two sub-blocks are coupled with each other.

First claim

What is claimed is:

1 . An electrostatic discharge (ESD) protection circuit using GaN devices, comprising:
a power high electron mobility transistor (HEMT) with a gate, a source and a drain, said source and said drain are coupled respectively to a first reference voltage and a second reference voltage; and an ESD protection block, comprising:
a first sub-block, comprising:
a first trigger with one terminal coupled to said gate;
a first Two-Dimensional Electron Gas (2DEG) resistor with one terminal coupled to another terminal of said first trigger;
a first LV-HEMT with a first gate, a first source and a first drain, said first gate is coupled to said another terminal of said first trigger and said terminal of said first 2DEG resistor, and said first source is coupled to said gate and said terminal of said first trigger; and
a first lateral field effect rectifier with one terminal coupled to said first gate,
said another terminal of said first trigger and said terminal of said first 2DEG resistor;

a second sub-block, comprising:
a second trigger with one terminal coupled to said source and said first reference voltage;
a second 2DEG resistor with one terminal coupled to another terminal of said second trigger;
a second LV-HEMT with a second gate, a second source and a second drain, said second gate
is coupled to said another terminal of said second trigger and said terminal of said second 2DEG resistor, and said second source is coupled to said source and
said first reference voltage; and
a second lateral field effect rectifier with one terminal coupled to said second gate,
said another terminal of said second trigger and said terminal of said second 2DEG resistor;

wherein another terminal of said first 2DEG resistor, another terminal of said second 2DEG resistor, another terminal of said first lateral field effect rectifier, another terminal of said second lateral field effect rectifier, said first drain and said second drain are coupled with each other.

2 . The ESD protection circuit using GaN devices of claim 1 , wherein said first trigger is a GaN capacitor, comprising:
a GaN substrate; an AlGaN layer on said GaN substrate; a p-GaN layer on said AlGaN layer and coupled with an anode; and a cathode on said GaN substrate and said AlGaN layer at one side of said p-GaN layer.

3 . The ESD protection circuit using GaN devices of claim 1 , wherein said second trigger is a GaN capacitor, comprising:
a GaN substrate; an AlGaN layer on said GaN substrate; a p-GaN layer on said AlGaN layer and coupled with an anode; and a cathode on said GaN substrate and said AlGaN layer at one side of said p-GaN layer.

4 . The ESD protection circuit using GaN devices of claim 1 , wherein said first trigger is a metal-insulator-metal capacitor, comprising:
a GaN substrate; an ion implant isolation layer on said GaN substrate; a passivation layer on said ion implant isolation layer; an anode metal layer in said passivation layer; and a cathode metal layer on said passivation layer.

5 . The ESD protection circuit using GaN devices of claim 1 , wherein said second trigger is a metal-insulator-metal capacitor, comprising:
a GaN substrate; an ion implant isolation layer on said GaN substrate; a passivation layer on said ion implant isolation layer; an anode metal layer in said passivation layer; and a cathode metal layer on said passivation layer.

6 . The ESD protection circuit using GaN devices of claim 1 , wherein said first trigger comprises at least one lateral field effect rectifier in serial connection, and each said lateral field effect rectifier comprises:
a GaN substrate; an AlGaN layer on said GaN substrate; a p-GaN layer on said AlGaN layer and coupled with a first anode; and a cathode and a second anode on said GaN substrate and said AlGaN layer respectively at two sides of said p-GaN layer, wherein cathode and said second anode are coupled respectively to said terminal and said another terminal of said first trigger, and said first anode is coupled to said second anode.

7 . The ESD protection circuit using GaN devices of claim 1 , wherein said second trigger comprises at least one lateral field effect rectifier in serial connection, and each said lateral field effect rectifier comprises:
a GaN substrate; an AlGaN layer on said GaN substrate; a p-GaN layer on said AlGaN layer and coupled with a first anode; and a cathode and a second anode on said GaN substrate and said AlGaN layer respectively at two sides of said p-GaN layer, wherein said cathode and said second anode are coupled respectively to said terminal and said another terminal of said second trigger, and said first anode is coupled to said second anode.

8 . The ESD protection circuit using GaN devices of claim 1 , wherein said first lateral field effect rectifier comprises:
a GaN substrate; an AlGaN layer on said GaN substrate; a p-GaN layer on said AlGaN layer and coupled with a first anode; and a cathode and a second anode on said GaN substrate and said AlGaN layer respectively at two sides of said p-GaN layer, wherein said cathode and said second anode are coupled respectively to said terminal and said another terminal of said first trigger, and said first anode is coupled to said second anode.

9 . The (ESD) protection circuit using GaN devices of claim 1 , wherein said second lateral field effect rectifier comprises:
a GaN substrate; an AlGaN layer on said GaN substrate; a p-GaN layer on said AlGaN layer and coupled with a first anode; and a cathode and a second anode on said GaN substrate and said AlGaN layer respectively at
two sides of said p-GaN layer, wherein said cathode and said second anode are coupled
respectively to said terminal and said another terminal of said second trigger, and said
first anode is coupled to said second anode
further comprising a main 2DEG resistor with one terminal coupled to said gate and with another terminal coupled to said terminal of said first trigger and said first source.

10 . The ESD protection circuit using GaN devices of claim 1 , wherein said main 2DEG resistor comprises: a GaN substrate; an AlGaN layer on said GaN substrate; and a high-voltage terminal and a low-voltage terminal on said GaN substrate and said AlGaN layer and coupled respectively to said another terminal and said terminal of said main 2DEG resistor.

11 . The ESD protection circuit using GaN devices of claim 1 , wherein said first 2DEG resistor comprises:
a GaN substrate; an AlGaN layer on said GaN substrate; and a high-voltage terminal and a low-voltage terminal on said GaN substrate and said AlGaN layer and coupled respectively to said terminal and said another terminal of said first 2DEG resistor.

12 . The ESD protection circuit using GaN devices of claim 1 , wherein said second 2DEG resistor comprises:
a GaN substrate; an AlGaN layer on said GaN substrate; and a high-voltage terminal and a low-voltage terminal on said GaN substrate and said AlGaN layer and coupled respectively to said terminal and said another terminal of said second 2DEG resistor.

13 . The ESD protection circuit using GaN devices of claim 1 , wherein said first LV-HEMT comprises:
a GaN substrate; an AlGaN layer on said GaN substrate; a p-GaN layer on said AlGaN layer and coupled with said first gate; and said first source and said first drain on said GaN substrate and said AlGaN layer respectively at two sides of said p-GaN layer.

14 . The ESD protection circuit using GaN devices of claim 1 , wherein said second LV-HEMT comprises:
a GaN substrate; an AlGaN laye

Assignees

• United Microelectronics Corp

Inventors

• Chang Yu-Hsuan
• Li Ching-Wei
• Lee Jih-San
• Tang Tien-Hao

Classifications

• H10D84/811 Primary

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D89/60 Primary

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H02H7/205

  for controlled semi-conductors which are not included in a specific circuit arrangement · CPC title