Solid-state imaging device and imaging apparatus

Patent metadata

Field	Value
Publication number	US-12587759-B2
Application number	US-202318543731-A
Country	US
Kind code	B2
Filing date	Dec 18, 2023
Priority date	Jun 22, 2021
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A solid-state imaging device includes a plurality of pixel circuits arranged in rows and columns; and a relief unit which includes N signal lines and n pixel circuits among the plurality of pixel circuits, N being an integer greater than or equal to 3, n being an integer less than or equal to N. Each of the n pixel circuits is connected to a group of at least two signal lines out of the N signal lines, and selectively outputs a pixel signal to one of the at least two signal lines included in the group; and n groups corresponding to the n pixel circuits have mutually different combinations of signal lines, the n groups each being the group.

First claim

The invention claimed is:

1 . A solid-state imaging device comprising:
a plurality of pixel circuits arranged in rows and columns; and a relief unit, wherein: the relief unit includes N signal lines and n pixel circuits among the plurality of pixel circuits, N being an integer greater than or equal to 3, n being an integer less than or equal to N, the n pixel circuits are included in one column, each of the n pixel circuits included in one column is connected to at least two signal lines out of the N signal lines, and selectively outputs a pixel signal to one of the at least two signal lines included, and the n pixel circuits included in one column have mutually different connection combinations of signal lines.

2 . The solid-state imaging device according to claim 1 , wherein
each of the n pixel circuits includes:
an amplification transistor that outputs a pixel signal; and
selection transistors of a total number equal to a total number of the at least two signal lines, and
the selection transistors each connect an output terminal of the amplification transistor and one of the at least two signal lines.

3 . The solid-state imaging device according to claim 1 , wherein
the N signal lines include n signal lines of a total number equal to a total number of n pixel signals and α redundant signal lines, α being an integer greater than or equal to 1, and each of the plurality of pixel circuits is connected to at least (1+α) signal lines.

4 . The solid-state imaging device according to claim 3 , wherein
an ith pixel circuit in the n pixel circuits is connected to, among the N signal lines, ith to (i+α)th signal lines in arrangement order in a column alignment direction, i being an integer from 1 to n.

5 . The solid-state imaging device according to claim 1 , wherein
the n pixel circuits output pixel signals in parallel, n being an integer less than N.

6 . The solid-state imaging device according to claim 1 , wherein
the N signal lines do not include a redundant signal line, and the n pixel circuits include at least one pixel circuit which outputs a pixel signal in a time-division manner from a signal line which is also connected to an other pixel circuit.

7 . The solid-state imaging device according to claim 5 , wherein
the N signal lines are divided into a first group and a second group, the first group includes n/2 signal lines and α signal lines out of the N signal lines, the second group includes n/2 signal lines different from the n/2 signal lines of the first group and the α signal lines identical to the α signal lines of the first group, the solid-state imaging device further comprises a first column circuit and a second column circuit for each column, the first column circuit is connected to signal lines that belong to the first group, the second column circuit is connected to signal lines that belong to the second group, and n/2 pixel circuits corresponding to the first group select a signal line to which a pixel signal is output, independently of n/2 pixel circuits corresponding to the second group.

8 . The solid-state imaging device according to claim 7 , further comprising:
a first switch and a second switch provided to each of the α signal lines, wherein the first switch switches between a connecting state in which one end of a corresponding signal line and the first column circuit are connected and a disconnecting state in which the one end of the corresponding signal line and the first column circuit are disconnected, the second switch switches between a connecting state in which an other end of the corresponding signal line and the second column circuit are connected and a disconnecting state in which the other end of the corresponding signal line and the second column circuit are disconnected, and the first switch and the second switch are not simultaneously in the connecting state.

9 . The solid-state imaging device according to claim 1 , further comprising:
a scanning circuit that scans the plurality of pixel circuits, wherein the scanning circuit controls, for the n pixel circuits, selection of a signal line to which a pixel signal is to be output.

10 . The solid-state imaging device according to claim 1 , further comprising:
a plurality of scanning circuits corresponding to a plurality of regions into which the plurality of pixel circuits are divided, and the plurality of scanning circuits independently control selection of a signal line to which a pixel signal is to be output.

11 . The solid-state imaging device according to claim 1 , further comprising:
a load element in at least two signal lines among the N signal lines, the load element being for adjusting a magnitude of a load.

12 . An imaging apparatus comprising:
the solid-state imaging device according to claim 1 which captures an image of an object; an imaging optical system that guides an incident light from the object to the solid-state imaging device; and a signal processor that processes an output signal from the solid-state imaging device.

13 . The solid-state imaging device according to claim 1 , wherein at least one signal line is commonly connected to two pixel circuits among the n pixel circuits included in one column.

Assignees

• Nuvoton Technology Corp Japan

Inventors

• Kito Takayasu
• Sumitani Norihiko

Classifications

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/703

  SSIS architectures incorporating pixels for producing signals other than image signals · CPC title

• H04N25/68 Primary

  applied to defects · CPC title

• H04N25/69 Primary

  SSIS comprising testing or correcting structures for circuits other than pixel cells · CPC title