Multiplexing distinct signals on a single pin of a memory device

Patent metadata

Field	Value
Publication number	US-12587418-B2
Application number	US-202217851533-A
Country	US
Kind code	B2
Filing date	Jun 28, 2022
Priority date	Oct 2, 2017
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

First claim

What is claimed is:

1 . A volatile memory system, comprising:
a bus; and a multiplexer circuit, wherein the volatile memory system supports multiple modulation schemes comprising a non-return-to zero (NRZ) scheme having two levels and a pulse-amplitude modulation (PAM) scheme having at least three levels, and wherein the volatile memory system is operable to:
generate, by the multiplexer circuit in accordance with the PAM scheme, a single symbol of a pulse-amplitude-modulated signal that indicates first information of a first type of metadata for a set of stored data and second information of a second type of metadata for the set of stored data, wherein the single symbol is generated based at least in part on a modulation scheme mode of the volatile memory system, wherein the pulse-amplitude-modulated signal has at least three levels, and wherein the second type of metadata is different than the first type of metadata;
transmit, in accordance with a first clock frequency and based at least in part on generating the single symbol of the pulse-amplitude-modulated signal that indicates the first information of the first type of metadata and the second information of the second type of metadata, the single symbol of the pulse-amplitude-modulated signal over the bus; and
switch from transmitting in accordance with the PAM scheme and the first clock frequency to transmitting in accordance with the NRZ scheme and a second clock frequency different than the first clock frequency.

2 . The volatile memory system of claim 1 , wherein the volatile memory system is operable to receive a request from a host device coupled with the volatile memory system.

3 . The volatile memory system of claim 2 , wherein the first information of the first type of metadata and the second information of the second type of metadata are associated with the request from the host device.

4 . The volatile memory system of claim 1 , wherein the first information of the first type of metadata and the second information of the second type of metadata are associated with a read operation.

5 . The volatile memory system of claim 1 , wherein the volatile memory system is coupled with a graphics processing unit (GPU).

6 . The volatile memory system of claim 1 , wherein the volatile memory system comprises a random access memory system.

7 . The volatile memory system of claim 1 , wherein the first information of the first type of metadata has a different logic value than the second information of the second type of metadata.

8 . The volatile memory system of claim 1 , wherein the first information of the first type of metadata and the second information of the second type of metadata are associated with a read command.

9 . A method, comprising:
generating, at a volatile memory system that supports multiple modulation schemes comprising a non-return-to zero (NRZ) scheme having two levels and a pulse-amplitude modulation (PAM) scheme having at least three levels, a single symbol of a pulse-amplitude-modulated signal that indicates first information of a first type of metadata for a set of stored data and second information of a second type of metadata for the set of stored data, wherein the single symbol is generated in accordance with the PAM scheme based at least in part on a modulation scheme mode of the volatile memory system, wherein the pulse-amplitude-modulated signal has at least three levels, and wherein the second type of metadata is different than the first type of metadata; transmitting, in accordance with a first clock frequency and based at least in part on generating the single symbol of the pulse-amplitude-modulated signal that indicates the first information of the first type of metadata and the second information of the second type of metadata, the single symbol of the pulse-amplitude-modulated signal over a bus coupled with the volatile memory system; and switching from transmitting in accordance with the PAM scheme and the first clock frequency to transmitting in accordance with the NRZ scheme and a second clock frequency different than the first clock frequency.

10 . The method of claim 9 , further comprising:
receiving a request from a host device coupled with the volatile memory system.

11 . The method of claim 10 , wherein the first information of the first type of metadata and the second information of the second type of metadata are associated with the request from the host device.

12 . The method of claim 9 , wherein the first information of the first type of metadata and the second information of the second type of metadata are associated with a read operation.

13 . The method of claim 9 ,
wherein the volatile memory system is coupled with a graphics processing unit (GPU).

14 . The method of claim 9 , wherein the volatile memory system comprises random access memory system.

15 . The method of claim 9 , wherein the first information of the first type of metadata has a different logic value than the second information of the second type of metadata.

16 . The method of claim 9 , wherein the first information of the first type of metadata and the second information of the second type of metadata are associated with a read command.

17 . An apparatus, comprising:
a first volatile memory die storing a set of data, wherein the apparatus supports multiple modulation schemes comprising a non-return-to zero (NRZ) scheme having two levels and a pulse-amplitude modulation (PAM) scheme having at least three levels, and wherein the apparatus is operable to:
generate a single symbol of a pulse-amplitude-modulated signal that indicates first information of a first type of metadata for the set of data and second information of a second type of metadata for the set of data, wherein the single symbol is generated in accordance with the PAM scheme based at least in part on a modulation scheme mode of the first volatile memory die, wherein the pulse-amplitude-modulated signal has at least three levels, and wherein the second type of metadata is different than the first type of metadata;
transmit, in accordance with a first clock frequency and based at least in part on generating the single symbol of the pulse-amplitude-modulated signal that comprises the first information of the first type of metadata and the second information of the second type of metadata, the single symbol of the pulse-amplitude-modulated signal over a bus; and
switch from transmitting in accordance with the PAM scheme and the first clock frequency to transmitting in accordance with the NRZ scheme and a second clock frequency different than the first clock frequency.

18 . The apparatus of claim 17 , wherein the apparatus is operable to receive a request from a host device, and wherein the first information of the first type of metadata and the second information of the second type of metadata are associated with the request from the host device.

Assignees

• Micron Technology Inc

Inventors

• Hasbun Robert Nasry
• Hollis Timothy M
• Wright Jeffrey P
• Gans Dean D

Classifications

• G11C2207/101

  Analog or multilevel bus · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C5/066 Primary

  Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals · CPC title