Non-volatile memory with multiple data resolutions
US-2025037783-A1 · Jan 30, 2025 · US
Memory device and operating method thereof
US12586643B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12586643-B2 |
| Application number | US-202418672190-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 23, 2024 |
| Priority date | Jan 16, 2024 |
| Publication date | Mar 24, 2026 |
| Grant date | Mar 24, 2026 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A memory device includes a first memory cell including channel, source and drain structures and a charge trap layer. When a first data bit has a first logic value and a voltage signal applied to the charge trap layer has a first voltage level, a current signal flowing through the channel structure has a first current level. When the first data bit has the first logic value and the voltage signal has a second voltage level, the current signal has a second current level. When the first data bit has a second logic value and the voltage signal has the first voltage level, the current signal has the second current level. When the first data bit has the second logic value and the voltage signal has the second voltage level, the current signal has the first current level.
First claim
Opening claim text (preview).
What is claimed is: 1 . A memory device, comprising a first memory cell configured to store a first data bit, the first memory cell comprising: a channel structure; a source structure contacting a first side of the channel structure; a drain structure contacting a second side of the channel structure; and a charge trap layer contacting a third side of the channel structure, wherein when the first data bit has a first logic value and a voltage signal applied to the charge…
Assignees
Inventors
Classifications
Physics · mapped topic
Electricity · mapped topic
Physics · mapped topic
- G11C15/046Primary
Physics · mapped topic
- G11C15/04Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US12586643B2 cover?
- A memory device includes a first memory cell including channel, source and drain structures and a charge trap layer. When a first data bit has a first logic value and a voltage signal applied to the charge trap layer has a first voltage level, a current signal flowing through the channel structure has a first current level. When the first data bit has the first logic value and the voltage signa…
- Who is the assignee on this patent?
- Macronix Int Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G11C15/046. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 24 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).