Faster computer memory access by reducing SLAT fragmentation

Patent metadata

Field	Value
Publication number	US-12585595-B2
Application number	US-202418403380-A
Country	US
Kind code	B2
Filing date	Jan 3, 2024
Priority date	Nov 21, 2018
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

To increase the speed with which a Second Layer Address Table (SLAT) is traversed, memory having the same access permissions is contiguously arranged such that one or more hierarchical levels of the SLAT need not be referenced, thereby resulting in more efficient SLAT traversal. “Slabs” of memory are established whose memory range is sufficiently large that reference to a hierarchically lower level table can be skipped and a hierarchically higher level table's entries can directly identify relevant memory addresses. Such slabs are aligned to avoid smaller intermediate memory ranges. The loading of code or data into memory is performed based on a next available memory location within a slab having equivalent access permissions, or, if such a slab is not available, or if an existing slab does not have a sufficient quantity of available memory remaining, a new slab with the proper access permissions is established.

First claim

We claim:

1 . A computing device comprising:
a processing unit; and volatile memory storing instructions that, when executed, perform operations comprising:
identifying physical memory of the volatile memory by traversing hierarchical levels of an address table; and
allocating a memory slab for a memory access directed to virtual memory corresponding to the physical memory, the memory slab comprising memory ranges including memory addresses that each have a same set of access permissions and the memory slab being coextensive with at least one of:
a first memory range sized to encompass ranges of memory at a first hierarchical level of the address table; or
a second memory range sized to encompass ranges of memory at a second hierarchical level of the address table that is higher in the hierarchical levels than the first hierarchical level.

2 . The computing device of claim 1 , further comprising:
a virtual operating system including a memory manager that implements a page table correlating virtual memory addresses to physical memory addresses, wherein the page table is different from the address table.

3 . The computing device of claim 1 , further comprising:
a virtual operating system including a slab allocator that allocates the memory slab and establishes:
memory ranges in a form of beginning and ending memory addresses; and
memory access permissions corresponding to the memory ranges.

4 . The computing device of claim 1 , wherein the address table is a Second Layer Address Table (SLAT) that delineates relationships between virtual memory addresses and physical memory addresses of the volatile memory.

5 . The computing device of claim 1 , wherein the first memory range represents a first memory page that is a contiguous range of memory of a first size.

6 . The computing device of claim 5 , wherein the second memory range represents a second memory page that is a contiguous range of memory of a second size that is larger than the first size.

7 . The computing device of claim 1 , wherein the first hierarchical level is one hierarchical level above a lowest hierarchical level of the address table.

8 . The computing device of claim 7 , wherein the second hierarchical level is at least two hierarchical levels above the lowest hierarchical level of the address table.

9 . The computing device of claim 7 , wherein the lowest hierarchical level of the address table includes entries representing a smallest individually quantity of memory manageable by the computing device.

10 . The computing device of claim 9 , wherein each entry of the entries represents a page of memory.

11 . The computing device of claim 10 , wherein access permissions for each page of memory is established on a page-by-page basis.

12 . The computing device of claim 1 , the operations further comprising:
providing an identifier of one or more address in the memory slab to a requestor of the memory access.

13 . The computing device of claim 12 , wherein the identifier is a pointer to memory addresses of the memory slab.

14 . The computing device of claim 12 , wherein the requestor of the memory access is a process that invoked a loading of data into the volatile memory.

15 . The computing device of claim 14 , wherein the process is associated with an application executing in a virtual machine operating in the computing device.

16 . A method comprising:
identifying physical memory of a volatile memory by traversing hierarchical levels of an address table; and allocating a memory slab for a memory access directed to virtual memory corresponding to the physical memory, the memory slab comprising memory ranges including memory addresses that each have a same set of access permissions and the memory slab being coextensive with at least one of:
a first memory range sized to encompass ranges of memory at a first hierarchical level of the address table; or
a second memory range sized to encompass ranges of memory at a second hierarchical level of the address table that is higher in the hierarchical levels than the first hierarchical level.

17 . The method of claim 16 , the method further comprising:
prior to identifying the physical memory, receiving a request for the memory access from a process executed by a virtual machine hosted by a host device that implements the volatile memory.

18 . The method of claim 17 , wherein the process perceives memory addresses referenced by the memory access as physical memory addresses.

19 . The method of claim 16 , wherein the first hierarchical level is a lowest hierarchical level of the address table.

20 . A system comprising:
a processing unit; volatile memory storing instructions that, when executed, perform operations comprising:
in response to a request to perform a memory access directed to virtual memory corresponding to physical memory of the volatile memory, identifying the physical memory by traversing hierarchical levels of an address table; and
allocating a memory slab for the memory access, the memory slab comprising memory ranges including memory addresses that each have a same set of access permissions and the memory slab being coextensive with at least one of:
a first memory range sized to encompass ranges of memory at a first hierarchical level of the address table; or
a second memory range sized to encompass ranges of memory at a second hierarchical level of the address table that is at least one hierarchical level above the first hierarchical level.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Bak Yevgeniy
• Iyigun Mehmet
• Lange Jonathan E

Classifications

• G06F2212/1024

  Latency reduction · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F2212/1052

  Security improvement · CPC title