Efficient error signaling by memory

Patent metadata

Field	Value
Publication number	US-12585407-B2
Application number	US-202418794882-A
Country	US
Kind code	B2
Filing date	Aug 5, 2024
Priority date	Jul 19, 2022
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

Methods, systems, and devices for efficient error signaling by memory are described. When executing a read operation, a memory device may perform an error control operation to detect errors in data associated with the read operation and transmit signaling indicating the data. The memory device may transmit signaling indicating a first or second value of an indicator of a combination error: the first value indicating that an error was detected in the data during the error control operation or a non-driven condition for transmitting the signaling indicating the data, and the second value indicating that no errors were detected in the data during the error control operation and that the read operation has been executed. The memory device may additionally store a value in a register indicating whether an indicated combination error corresponds to errors being detected in the data, a non-driven condition, or both.

First claim

What is claimed is:

1 . A memory device, comprising:
one or more memory arrays; and processing circuitry coupled with the one or more memory arrays and configured to cause the memory device to:
perform, based at least in part on executing a read operation, an error control operation to detect one or more errors in data associated with the read operation;
transmit, to a host system, first signaling indicating the data associated with the read operation based at least in part on performing the error control operation;
transmit, to the host system, second signaling comprising an indicator of a combination error having a first state, wherein the first state indicates a non-driven condition for the first signaling; and
transmit, to the host system, third signaling comprising the indicator having the first state based at least in part on detecting the one or more errors in the data during the error control operation.

2 . The memory device of claim 1 , wherein, to transmit the second signaling, the processing circuitry is further configured to cause the memory device to:
store, at a register, a first value corresponding to the first state to indicate the non-driven condition.

3 . The memory device of claim 1 , wherein, to transmit the third signaling, the processing circuitry is further configured to cause the memory device to:
store, at a register, a first value corresponding to the first state to indicate the one or more errors in the data during the error control operation.

4 . The memory device of claim 1 , wherein the processing circuitry is further configured to cause the memory device to:
store a second value corresponding to a second state in a register at the memory device, wherein the second value indicates that no errors are detected during the error control operation, an absence of the non-driven condition for the first signaling, or both.

5 . The memory device of claim 1 , wherein the processing circuitry is further configured to cause the memory device to:
store a third value corresponding to a third state in a register at the memory device, wherein the third value indicates that no errors are detected during the error control operation and the non-driven condition for the first signaling.

6 . The memory device of claim 1 , wherein, to transmit the second signaling, the processing circuitry is further configured to cause the memory device to:
output a first voltage level over a pin of the memory device to indicate the non-driven condition for the first signaling, wherein the first voltage level corresponds to a level of a termination voltage of the pin.

7 . The memory device of claim 6 , wherein, to transmit the third signaling, the processing circuitry is further configured to cause the memory device to:
output a first voltage level over a pin of the memory device to indicate the one or more errors detected in the data during the error control operation, wherein the first voltage level corresponds to a level of a termination voltage of the pin.

8 . The memory device of claim 7 , wherein the processing circuitry is further configured to cause the memory device to:
output a second voltage level over a pin of the memory device to indicate that the read operation has been executed and that no errors were detected in the data during the error control operation, wherein the second voltage level is different from the first voltage level.

9 . The memory device of claim 8 , wherein in an idle state, the pin is not driven to the first voltage level or the second voltage level.

10 . The memory device of claim 1 , wherein the non- driven condition is associated with a transmission of data corresponding to the read operation.

11 . The memory device of claim 1 , wherein:
transmitting the first signaling comprises transmitting the first signaling via one or more first pins of the memory device; and transmitting the second signaling comprises transmitting the second signaling via one or more second pins of the memory device, the one or more second pins different from the one or more first pins.

12 . The memory device of claim 11 , wherein the processing circuitry is further configured to cause the memory device to:
generate, based at least in part on performing the error control operation, error control information associated with the data; and transmit, via the one or more second pins at the memory device, third signaling indicating the error control information associated with the data.

13 . The memory device of claim 1 , wherein:
transmitting the first signaling comprises transmitting the first signaling via one or more pins at the memory device; and transmitting the second signaling comprises transmitting the second signaling via the one or more pins at the memory device.

14 . A host system, comprising:
one or more interfaces comprising one or more signal paths operatable for communications with one or more memory systems; and processing circuitry coupled with the one or more interfaces and configured to cause the host system to:
transmit a read command to a memory device;
receive, from the memory device, first signaling indicating data associated with the read command;
receive, from the memory device, second signaling comprising an indicator of a combination error having a first state, wherein the first state indicates a non-driven condition for the first signaling; and
receive, from the memory device, third signaling comprising the indicator having the first state based at least in part on one or more errors in the data being detected by the memory device during an error control operation.

15 . The host system of claim 14 , wherein the processing circuitry is further configured to cause the host system to:
read, from a register, a first value indicating the one or more errors detected in the data, wherein the indicator of the combination error is selected from the first value and a second value, wherein the second value indicates that the read command has been executed and that no errors were detected in the data during the error control operation.

16 . The host system of claim 14 , wherein the processing circuitry is further configured to cause the host system to:
read a value from a register based at least in part on reception of the third signaling comprising the indicator of the combination error having the first state, wherein the value indicates that the combination error comprises the one or more errors detected in the data during the error control operation and the non-driven condition for the first signaling.

17 . The host system of claim 14 , wherein the processing circuitry is further configured to cause the host system to:
read a value from a register at the host system based at least in part on reception of the third signaling comprising the indicator of the combination error having the first state, wherein the value indicates that the combination error comprises the one or more errors detected in the data during the error control operation and that the read command has been executed.

18 . The host system of claim 14 , wherein the processing circuitry is further configured to cause the host system to:
receive the second signaling and the third signaling via a pin that is separate from a set of pins used for receiving the first signaling.

19 . The host system of claim 14 , wherein, to receive the second signaling, the processing circuitry is further configured to cause the host system to:
receive a first voltage level over a pin of the host s

Assignees

• Micron Technology Inc

Inventors

• Buch Steffen
• Hein Thomas

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title